Lines Matching refs:WREG32
69 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch); in radeon_atom_set_backlight_level_to_reg()
71 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch); in radeon_atom_set_backlight_level_to_reg()
1554 WREG32(reg, (ATOM_S3_TV1_ACTIVE | in atombios_yuv_setup()
1557 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24))); in atombios_yuv_setup()
1559 WREG32(reg, 0); in atombios_yuv_setup()
1567 WREG32(reg, temp); in atombios_yuv_setup()
1628 WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE); in radeon_atom_encoder_dpms_avivo()
1630 WREG32(RADEON_BIOS_3_SCRATCH, reg); in radeon_atom_encoder_dpms_avivo()
2071 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control); in atombios_apply_encoder_quirks()
2080 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, in atombios_apply_encoder_quirks()
2083 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0); in atombios_apply_encoder_quirks()
2086 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, in atombios_apply_encoder_quirks()
2089 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0); in atombios_apply_encoder_quirks()
2092 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, in atombios_apply_encoder_quirks()
2095 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); in atombios_apply_encoder_quirks()