Lines Matching refs:RREG32
170 *val = RREG32(reg); in cik_get_allowed_info_register()
224 (void)RREG32(PCIE_INDEX); in cik_pciep_rreg()
225 r = RREG32(PCIE_DATA); in cik_pciep_rreg()
236 (void)RREG32(PCIE_INDEX); in cik_pciep_wreg()
238 (void)RREG32(PCIE_DATA); in cik_pciep_wreg()
1885 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK; in ci_mc_load_microcode()
1889 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); in ci_mc_load_microcode()
1908 tmp = RREG32(MC_SEQ_MISC0); in ci_mc_load_microcode()
1931 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0) in ci_mc_load_microcode()
1936 if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1) in ci_mc_load_microcode()
3436 data = RREG32(CC_RB_BACKEND_DISABLE); in cik_get_rb_disabled()
3441 data |= RREG32(GC_USER_RB_BACKEND_DISABLE); in cik_get_rb_disabled()
3533 u32 gb_addr_config = RREG32(GB_ADDR_CONFIG); in cik_gpu_init()
3654 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); in cik_gpu_init()
3655 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); in cik_gpu_init()
3750 tmp = RREG32(SPI_CONFIG_CNTL); in cik_gpu_init()
3758 tmp = RREG32(DB_DEBUG2) & ~0xf00fffff; in cik_gpu_init()
3762 tmp = RREG32(DB_DEBUG3) & ~0x0002021c; in cik_gpu_init()
3766 tmp = RREG32(CB_HW_CONTROL) & ~0x00010000; in cik_gpu_init()
3792 tmp = RREG32(HDP_MISC_CNTL); in cik_gpu_init()
3796 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); in cik_gpu_init()
3867 tmp = RREG32(scratch); in cik_ring_test()
4209 tmp = RREG32(scratch); in cik_ib_test()
4515 rptr = RREG32(CP_RB0_RPTR); in cik_gfx_get_rptr()
4525 wptr = RREG32(CP_RB0_WPTR); in cik_gfx_get_wptr()
4534 (void)RREG32(CP_RB0_WPTR); in cik_gfx_set_wptr()
4547 rptr = RREG32(CP_HQD_PQ_RPTR); in cik_compute_get_rptr()
4566 wptr = RREG32(CP_HQD_PQ_WPTR); in cik_compute_get_wptr()
4589 tmp = RREG32(CP_PQ_WPTR_POLL_CNTL); in cik_compute_stop()
4593 if (RREG32(CP_HQD_ACTIVE) & 1) { in cik_compute_stop()
4596 if (!(RREG32(CP_HQD_ACTIVE) & 1)) in cik_compute_stop()
4922 tmp = RREG32(CP_CPF_DEBUG); in cik_cp_compute_resume()
4941 tmp = RREG32(CP_HPD_EOP_CONTROL); in cik_cp_compute_resume()
5002 tmp = RREG32(CP_PQ_WPTR_POLL_CNTL); in cik_cp_compute_resume()
5008 RREG32(CP_HQD_PQ_DOORBELL_CONTROL); in cik_cp_compute_resume()
5020 if (RREG32(CP_HQD_ACTIVE) & 1) { in cik_cp_compute_resume()
5023 if (!(RREG32(CP_HQD_ACTIVE) & 1)) in cik_cp_compute_resume()
5038 mqd->queue_state.cp_mqd_control = RREG32(CP_MQD_CONTROL); in cik_cp_compute_resume()
5050 mqd->queue_state.cp_hqd_pq_control = RREG32(CP_HQD_PQ_CONTROL); in cik_cp_compute_resume()
5094 RREG32(CP_HQD_PQ_DOORBELL_CONTROL); in cik_cp_compute_resume()
5112 mqd->queue_state.cp_hqd_pq_rptr = RREG32(CP_HQD_PQ_RPTR); in cik_cp_compute_resume()
5188 RREG32(GRBM_STATUS)); in cik_print_gpu_status_regs()
5190 RREG32(GRBM_STATUS2)); in cik_print_gpu_status_regs()
5192 RREG32(GRBM_STATUS_SE0)); in cik_print_gpu_status_regs()
5194 RREG32(GRBM_STATUS_SE1)); in cik_print_gpu_status_regs()
5196 RREG32(GRBM_STATUS_SE2)); in cik_print_gpu_status_regs()
5198 RREG32(GRBM_STATUS_SE3)); in cik_print_gpu_status_regs()
5200 RREG32(SRBM_STATUS)); in cik_print_gpu_status_regs()
5202 RREG32(SRBM_STATUS2)); in cik_print_gpu_status_regs()
5204 RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET)); in cik_print_gpu_status_regs()
5206 RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); in cik_print_gpu_status_regs()
5207 dev_info(rdev->dev, " CP_STAT = 0x%08x\n", RREG32(CP_STAT)); in cik_print_gpu_status_regs()
5209 RREG32(CP_STALLED_STAT1)); in cik_print_gpu_status_regs()
5211 RREG32(CP_STALLED_STAT2)); in cik_print_gpu_status_regs()
5213 RREG32(CP_STALLED_STAT3)); in cik_print_gpu_status_regs()
5215 RREG32(CP_CPF_BUSY_STAT)); in cik_print_gpu_status_regs()
5217 RREG32(CP_CPF_STALLED_STAT1)); in cik_print_gpu_status_regs()
5218 dev_info(rdev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(CP_CPF_STATUS)); in cik_print_gpu_status_regs()
5219 dev_info(rdev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(CP_CPC_BUSY_STAT)); in cik_print_gpu_status_regs()
5221 RREG32(CP_CPC_STALLED_STAT1)); in cik_print_gpu_status_regs()
5222 dev_info(rdev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(CP_CPC_STATUS)); in cik_print_gpu_status_regs()
5240 tmp = RREG32(GRBM_STATUS); in cik_gpu_check_soft_reset()
5253 tmp = RREG32(GRBM_STATUS2); in cik_gpu_check_soft_reset()
5258 tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET); in cik_gpu_check_soft_reset()
5263 tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); in cik_gpu_check_soft_reset()
5268 tmp = RREG32(SRBM_STATUS2); in cik_gpu_check_soft_reset()
5276 tmp = RREG32(SRBM_STATUS); in cik_gpu_check_soft_reset()
5327 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR)); in cik_gpu_soft_reset()
5329 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS)); in cik_gpu_soft_reset()
5346 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_soft_reset()
5352 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_soft_reset()
5401 tmp = RREG32(GRBM_SOFT_RESET); in cik_gpu_soft_reset()
5405 tmp = RREG32(GRBM_SOFT_RESET); in cik_gpu_soft_reset()
5411 tmp = RREG32(GRBM_SOFT_RESET); in cik_gpu_soft_reset()
5415 tmp = RREG32(SRBM_SOFT_RESET); in cik_gpu_soft_reset()
5419 tmp = RREG32(SRBM_SOFT_RESET); in cik_gpu_soft_reset()
5425 tmp = RREG32(SRBM_SOFT_RESET); in cik_gpu_soft_reset()
5446 save->gmcon_reng_execute = RREG32(GMCON_RENG_EXECUTE); in kv_save_regs_for_reset()
5447 save->gmcon_misc = RREG32(GMCON_MISC); in kv_save_regs_for_reset()
5448 save->gmcon_misc3 = RREG32(GMCON_MISC3); in kv_save_regs_for_reset()
5549 tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET); in cik_gpu_pci_config_reset()
5553 tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET); in cik_gpu_pci_config_reset()
5581 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) in cik_gpu_pci_config_reset()
5721 tmp = RREG32(MC_ARB_RAMCFG); in cik_mc_init()
5727 tmp = RREG32(MC_SHARED_CHMAP); in cik_mc_init()
5763 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; in cik_mc_init()
5764 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; in cik_mc_init()
5904 u32 tmp = RREG32(CHUB_CONTROL); in cik_pcie_gart_enable()
5956 rdev->vm_manager.saved_table_addr[i] = RREG32(reg); in cik_pcie_gart_disable()
6032 u64 tmp = RREG32(MC_VM_FB_OFFSET); in cik_vm_init()
6172 u32 tmp = RREG32(CP_INT_CNTL_RING0); in cik_enable_gui_idle_interrupt()
6185 tmp = RREG32(RLC_LB_CNTL); in cik_enable_lbpw()
6203 if (RREG32(RLC_SERDES_CU_MASTER_BUSY) == 0) in cik_wait_for_rlc_serdes()
6214 if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0) in cik_wait_for_rlc_serdes()
6224 tmp = RREG32(RLC_CNTL); in cik_update_rlc()
6233 orig = data = RREG32(RLC_CNTL); in cik_halt_rlc()
6242 if ((RREG32(RLC_GPM_STAT) & RLC_GPM_BUSY) == 0) in cik_halt_rlc()
6262 if ((RREG32(RLC_GPM_STAT) & mask) == mask) in cik_enter_rlc_safe_mode()
6268 if ((RREG32(RLC_GPR_REG2) & REQ) == 0) in cik_enter_rlc_safe_mode()
6333 tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc; in cik_rlc_resume()
6410 orig = data = RREG32(RLC_CGCG_CGLS_CTRL); in cik_enable_cgcg()
6431 RREG32(CB_CGTT_SCLK_CTRL); in cik_enable_cgcg()
6432 RREG32(CB_CGTT_SCLK_CTRL); in cik_enable_cgcg()
6433 RREG32(CB_CGTT_SCLK_CTRL); in cik_enable_cgcg()
6434 RREG32(CB_CGTT_SCLK_CTRL); in cik_enable_cgcg()
6451 orig = data = RREG32(CP_MEM_SLP_CNTL); in cik_enable_mgcg()
6458 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); in cik_enable_mgcg()
6477 orig = data = RREG32(CGTS_SM_CTRL_REG); in cik_enable_mgcg()
6492 orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE); in cik_enable_mgcg()
6497 data = RREG32(RLC_MEM_SLP_CNTL); in cik_enable_mgcg()
6503 data = RREG32(CP_MEM_SLP_CNTL); in cik_enable_mgcg()
6509 orig = data = RREG32(CGTS_SM_CTRL_REG); in cik_enable_mgcg()
6548 orig = data = RREG32(mc_cg_registers[i]); in cik_enable_mc_ls()
6565 orig = data = RREG32(mc_cg_registers[i]); in cik_enable_mc_mgcg()
6584 orig = data = RREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
6589 orig = data = RREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgcg()
6602 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgls()
6607 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgls()
6612 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); in cik_enable_sdma_mgls()
6617 orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); in cik_enable_sdma_mgls()
6634 orig = data = RREG32(UVD_CGC_CTRL); in cik_enable_uvd_mgcg()
6643 orig = data = RREG32(UVD_CGC_CTRL); in cik_enable_uvd_mgcg()
6673 orig = data = RREG32(HDP_HOST_PATH_CNTL); in cik_enable_hdp_mgcg()
6689 orig = data = RREG32(HDP_MEM_POWER_LS); in cik_enable_hdp_ls()
6779 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_sck_slowdown_on_pu()
6793 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_sck_slowdown_on_pd()
6806 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_cp_pg()
6819 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_gds_pg()
6922 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_gfx_cgpg()
6927 orig = data = RREG32(RLC_AUTO_PG_CTRL); in cik_enable_gfx_cgpg()
6932 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_gfx_cgpg()
6937 orig = data = RREG32(RLC_AUTO_PG_CTRL); in cik_enable_gfx_cgpg()
6942 data = RREG32(DB_RENDER_CONTROL); in cik_enable_gfx_cgpg()
6953 tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG); in cik_get_cu_active_bitmap()
6954 tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG); in cik_get_cu_active_bitmap()
6998 tmp = RREG32(RLC_MAX_PG_CU); in cik_init_ao_cu_mask()
7009 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_gfx_static_mgpg()
7023 orig = data = RREG32(RLC_PG_CNTL); in cik_enable_gfx_dynamic_mgpg()
7056 orig = data = RREG32(RLC_PG_CNTL); in cik_init_gfx_cgpg()
7064 data = RREG32(CP_RB_WPTR_POLL_CNTL); in cik_init_gfx_cgpg()
7072 data = RREG32(RLC_PG_DELAY_2); in cik_init_gfx_cgpg()
7077 data = RREG32(RLC_AUTO_PG_CTRL); in cik_init_gfx_cgpg()
7238 u32 ih_cntl = RREG32(IH_CNTL); in cik_enable_interrupts()
7239 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in cik_enable_interrupts()
7257 u32 ih_rb_cntl = RREG32(IH_RB_CNTL); in cik_disable_interrupts()
7258 u32 ih_cntl = RREG32(IH_CNTL); in cik_disable_interrupts()
7283 tmp = RREG32(CP_INT_CNTL_RING0) & in cik_disable_interrupt_state()
7287 tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_disable_interrupt_state()
7289 tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_disable_interrupt_state()
7333 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
7335 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
7337 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
7339 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
7341 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
7343 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
7383 interrupt_cntl = RREG32(INTERRUPT_CNTL); in cik_irq_init()
7460 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & in cik_irq_set()
7464 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7465 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7466 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7467 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7468 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7469 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7471 dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_irq_set()
7472 dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in cik_irq_set()
7474 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7626 RREG32(SRBM_STATUS); in cik_irq_set()
7644 rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS); in cik_irq_ack()
7645 rdev->irq.stat_regs.cik.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); in cik_irq_ack()
7646 rdev->irq.stat_regs.cik.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); in cik_irq_ack()
7647 rdev->irq.stat_regs.cik.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); in cik_irq_ack()
7648 rdev->irq.stat_regs.cik.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); in cik_irq_ack()
7649 rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); in cik_irq_ack()
7650 rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6); in cik_irq_ack()
7652 rdev->irq.stat_regs.cik.d1grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7654 rdev->irq.stat_regs.cik.d2grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7657 rdev->irq.stat_regs.cik.d3grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7659 rdev->irq.stat_regs.cik.d4grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7663 rdev->irq.stat_regs.cik.d5grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7665 rdev->irq.stat_regs.cik.d6grph_int = RREG32(GRPH_INT_STATUS + in cik_irq_ack()
7719 tmp = RREG32(DC_HPD1_INT_CONTROL); in cik_irq_ack()
7724 tmp = RREG32(DC_HPD2_INT_CONTROL); in cik_irq_ack()
7729 tmp = RREG32(DC_HPD3_INT_CONTROL); in cik_irq_ack()
7734 tmp = RREG32(DC_HPD4_INT_CONTROL); in cik_irq_ack()
7739 tmp = RREG32(DC_HPD5_INT_CONTROL); in cik_irq_ack()
7744 tmp = RREG32(DC_HPD5_INT_CONTROL); in cik_irq_ack()
7749 tmp = RREG32(DC_HPD1_INT_CONTROL); in cik_irq_ack()
7754 tmp = RREG32(DC_HPD2_INT_CONTROL); in cik_irq_ack()
7759 tmp = RREG32(DC_HPD3_INT_CONTROL); in cik_irq_ack()
7764 tmp = RREG32(DC_HPD4_INT_CONTROL); in cik_irq_ack()
7769 tmp = RREG32(DC_HPD5_INT_CONTROL); in cik_irq_ack()
7774 tmp = RREG32(DC_HPD5_INT_CONTROL); in cik_irq_ack()
7843 wptr = RREG32(IH_RB_WPTR); in cik_get_ih_wptr()
7854 tmp = RREG32(IH_RB_CNTL); in cik_get_ih_wptr()
8245 DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); in cik_irq_process()
8254 addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR); in cik_irq_process()
8255 status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS); in cik_irq_process()
8256 mc_client = RREG32(VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT); in cik_irq_process()
9112 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in dce8_line_buffer_adjust()
9145 u32 tmp = RREG32(MC_SHARED_CHMAP); in cik_get_number_of_dram_channels()
9611 wm_mask = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset); in dce8_program_watermarks()
9620 tmp = RREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset); in dce8_program_watermarks()
9680 clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) | in cik_get_gpu_clock_counter()
9681 ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL); in cik_get_gpu_clock_counter()