167 	case (SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET):  in cik_get_allowed_info_register()
3718 	WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70);  in cik_gpu_init()
5206 		 RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));  in cik_print_gpu_status_regs()
5263 	tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);  in cik_gpu_check_soft_reset()
5352 		tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);  in cik_gpu_soft_reset()
5354 		WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);  in cik_gpu_soft_reset()
5553 	tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);  in cik_gpu_pci_config_reset()
5555 	WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);  in cik_gpu_pci_config_reset()
5922 		WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA1_REGISTER_OFFSET, 0);  in cik_pcie_gart_enable()
5923 		WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0);  in cik_pcie_gart_enable()
6582 		WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100);  in cik_enable_sdma_mgcg()
6589 		orig = data = RREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET);  in cik_enable_sdma_mgcg()
6592 			WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data);  in cik_enable_sdma_mgcg()
6607 		orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);  in cik_enable_sdma_mgls()
6610 			WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);  in cik_enable_sdma_mgls()
6617 		orig = data = RREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET);  in cik_enable_sdma_mgls()
6620 			WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);  in cik_enable_sdma_mgls()
7289 	tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;  in cik_disable_interrupt_state()
7290 	WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp);  in cik_disable_interrupt_state()
7472 	dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;  in cik_irq_set()
7582 	WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1);  in cik_irq_set()