Lines Matching refs:WREG32
223 WREG32(PCIE_INDEX, reg); in cik_pciep_rreg()
235 WREG32(PCIE_INDEX, reg); in cik_pciep_wreg()
237 WREG32(PCIE_DATA, v); in cik_pciep_wreg()
1831 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl); in cik_srbm_select()
1890 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); in ci_mc_load_microcode()
1894 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ci_mc_load_microcode()
1895 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); in ci_mc_load_microcode()
1900 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); in ci_mc_load_microcode()
1901 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); in ci_mc_load_microcode()
1903 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); in ci_mc_load_microcode()
1904 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); in ci_mc_load_microcode()
1910 WREG32(MC_SEQ_IO_DEBUG_INDEX, 5); in ci_mc_load_microcode()
1911 WREG32(MC_SEQ_IO_DEBUG_DATA, 0x00000023); in ci_mc_load_microcode()
1912 WREG32(MC_SEQ_IO_DEBUG_INDEX, 9); in ci_mc_load_microcode()
1913 WREG32(MC_SEQ_IO_DEBUG_DATA, 0x000001f0); in ci_mc_load_microcode()
1919 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); in ci_mc_load_microcode()
1921 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); in ci_mc_load_microcode()
1925 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in ci_mc_load_microcode()
1926 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); in ci_mc_load_microcode()
1927 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); in ci_mc_load_microcode()
1942 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); in ci_mc_load_microcode()
2473 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
2566 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
2696 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
2789 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
2920 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
3050 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
3144 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
3274 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
3367 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
3397 WREG32(GRBM_GFX_INDEX, data); in cik_select_se_sh()
3517 WREG32(PA_SC_RASTER_CONFIG, data); in cik_setup_rb()
3641 WREG32((0x2c14 + j), 0x00000000); in cik_gpu_init()
3642 WREG32((0x2c18 + j), 0x00000000); in cik_gpu_init()
3643 WREG32((0x2c1c + j), 0x00000000); in cik_gpu_init()
3644 WREG32((0x2c20 + j), 0x00000000); in cik_gpu_init()
3645 WREG32((0x2c24 + j), 0x00000000); in cik_gpu_init()
3648 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); in cik_gpu_init()
3649 WREG32(SRBM_INT_CNTL, 0x1); in cik_gpu_init()
3650 WREG32(SRBM_INT_ACK, 0x1); in cik_gpu_init()
3652 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); in cik_gpu_init()
3714 WREG32(GB_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3715 WREG32(HDP_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3716 WREG32(DMIF_ADDR_CALC, gb_addr_config); in cik_gpu_init()
3717 WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70); in cik_gpu_init()
3718 WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70); in cik_gpu_init()
3719 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3720 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3721 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); in cik_gpu_init()
3738 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); in cik_gpu_init()
3746 WREG32(SX_DEBUG_1, 0x20); in cik_gpu_init()
3748 WREG32(TA_CNTL_AUX, 0x00010000); in cik_gpu_init()
3752 WREG32(SPI_CONFIG_CNTL, tmp); in cik_gpu_init()
3754 WREG32(SQ_CONFIG, 1); in cik_gpu_init()
3756 WREG32(DB_DEBUG, 0); in cik_gpu_init()
3760 WREG32(DB_DEBUG2, tmp); in cik_gpu_init()
3764 WREG32(DB_DEBUG3, tmp); in cik_gpu_init()
3768 WREG32(CB_HW_CONTROL, tmp); in cik_gpu_init()
3770 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); in cik_gpu_init()
3772 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) | in cik_gpu_init()
3777 WREG32(VGT_NUM_INSTANCES, 1); in cik_gpu_init()
3779 WREG32(CP_PERFMON_CNTL, 0); in cik_gpu_init()
3781 WREG32(SQ_CONFIG, 0); in cik_gpu_init()
3783 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | in cik_gpu_init()
3786 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | in cik_gpu_init()
3789 WREG32(VGT_GS_VERTEX_REUSE, 16); in cik_gpu_init()
3790 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); in cik_gpu_init()
3794 WREG32(HDP_MISC_CNTL, tmp); in cik_gpu_init()
3797 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); in cik_gpu_init()
3799 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); in cik_gpu_init()
3800 WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER); in cik_gpu_init()
3854 WREG32(scratch, 0xCAFEDEAD); in cik_ring_test()
4183 WREG32(scratch, 0xCAFEDEAD); in cik_ib_test()
4260 WREG32(CP_ME_CNTL, 0); in cik_cp_gfx_enable()
4264 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); in cik_cp_gfx_enable()
4305 WREG32(CP_PFP_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
4307 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
4308 WREG32(CP_PFP_UCODE_ADDR, le32_to_cpu(pfp_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
4314 WREG32(CP_CE_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
4316 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
4317 WREG32(CP_CE_UCODE_ADDR, le32_to_cpu(ce_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
4323 WREG32(CP_ME_RAM_WADDR, 0); in cik_cp_gfx_load_microcode()
4325 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
4326 WREG32(CP_ME_RAM_WADDR, le32_to_cpu(me_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
4327 WREG32(CP_ME_RAM_RADDR, le32_to_cpu(me_hdr->header.ucode_version)); in cik_cp_gfx_load_microcode()
4333 WREG32(CP_PFP_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
4335 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
4336 WREG32(CP_PFP_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
4340 WREG32(CP_CE_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
4342 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
4343 WREG32(CP_CE_UCODE_ADDR, 0); in cik_cp_gfx_load_microcode()
4347 WREG32(CP_ME_RAM_WADDR, 0); in cik_cp_gfx_load_microcode()
4349 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); in cik_cp_gfx_load_microcode()
4350 WREG32(CP_ME_RAM_WADDR, 0); in cik_cp_gfx_load_microcode()
4371 WREG32(CP_MAX_CONTEXT, rdev->config.cik.max_hw_contexts - 1); in cik_cp_gfx_start()
4372 WREG32(CP_ENDIAN_SWAP, 0); in cik_cp_gfx_start()
4373 WREG32(CP_DEVICE_ID, 1); in cik_cp_gfx_start()
4448 WREG32(CP_SEM_WAIT_TIMER, 0x0); in cik_cp_gfx_resume()
4450 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); in cik_cp_gfx_resume()
4453 WREG32(CP_RB_WPTR_DELAY, 0); in cik_cp_gfx_resume()
4456 WREG32(CP_RB_VMID, 0); in cik_cp_gfx_resume()
4458 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in cik_cp_gfx_resume()
4468 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
4471 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in cik_cp_gfx_resume()
4473 WREG32(CP_RB0_WPTR, ring->wptr); in cik_cp_gfx_resume()
4476 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); in cik_cp_gfx_resume()
4477 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in cik_cp_gfx_resume()
4480 WREG32(SCRATCH_UMSK, 0); in cik_cp_gfx_resume()
4486 WREG32(CP_RB0_CNTL, tmp); in cik_cp_gfx_resume()
4489 WREG32(CP_RB0_BASE, rb_addr); in cik_cp_gfx_resume()
4490 WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr)); in cik_cp_gfx_resume()
4533 WREG32(CP_RB0_WPTR, ring->wptr); in cik_gfx_set_wptr()
4591 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp); in cik_compute_stop()
4594 WREG32(CP_HQD_DEQUEUE_REQUEST, 1); in cik_compute_stop()
4600 WREG32(CP_HQD_DEQUEUE_REQUEST, 0); in cik_compute_stop()
4601 WREG32(CP_HQD_PQ_RPTR, 0); in cik_compute_stop()
4602 WREG32(CP_HQD_PQ_WPTR, 0); in cik_compute_stop()
4618 WREG32(CP_MEC_CNTL, 0); in cik_cp_compute_enable()
4629 WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT)); in cik_cp_compute_enable()
4665 WREG32(CP_MEC_ME1_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4667 WREG32(CP_MEC_ME1_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_cp_compute_load_microcode()
4668 WREG32(CP_MEC_ME1_UCODE_ADDR, le32_to_cpu(mec_hdr->header.ucode_version)); in cik_cp_compute_load_microcode()
4679 WREG32(CP_MEC_ME2_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4681 WREG32(CP_MEC_ME2_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_cp_compute_load_microcode()
4682 WREG32(CP_MEC_ME2_UCODE_ADDR, le32_to_cpu(mec2_hdr->header.ucode_version)); in cik_cp_compute_load_microcode()
4689 WREG32(CP_MEC_ME1_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4691 WREG32(CP_MEC_ME1_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_cp_compute_load_microcode()
4692 WREG32(CP_MEC_ME1_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4697 WREG32(CP_MEC_ME2_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4699 WREG32(CP_MEC_ME2_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_cp_compute_load_microcode()
4700 WREG32(CP_MEC_ME2_UCODE_ADDR, 0); in cik_cp_compute_load_microcode()
4924 WREG32(CP_CPF_DEBUG, tmp); in cik_cp_compute_resume()
4934 WREG32(CP_HPD_EOP_BASE_ADDR, eop_gpu_addr >> 8); in cik_cp_compute_resume()
4935 WREG32(CP_HPD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr) >> 8); in cik_cp_compute_resume()
4938 WREG32(CP_HPD_EOP_VMID, 0); in cik_cp_compute_resume()
4944 WREG32(CP_HPD_EOP_CONTROL, tmp); in cik_cp_compute_resume()
5004 WREG32(CP_PQ_WPTR_POLL_CNTL, tmp); in cik_cp_compute_resume()
5013 WREG32(CP_HQD_PQ_DOORBELL_CONTROL, in cik_cp_compute_resume()
5021 WREG32(CP_HQD_DEQUEUE_REQUEST, 1); in cik_cp_compute_resume()
5027 WREG32(CP_HQD_DEQUEUE_REQUEST, mqd->queue_state.cp_hqd_dequeue_request); in cik_cp_compute_resume()
5028 WREG32(CP_HQD_PQ_RPTR, mqd->queue_state.cp_hqd_pq_rptr); in cik_cp_compute_resume()
5029 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); in cik_cp_compute_resume()
5035 WREG32(CP_MQD_BASE_ADDR, mqd->queue_state.cp_mqd_base_addr); in cik_cp_compute_resume()
5036 WREG32(CP_MQD_BASE_ADDR_HI, mqd->queue_state.cp_mqd_base_addr_hi); in cik_cp_compute_resume()
5040 WREG32(CP_MQD_CONTROL, mqd->queue_state.cp_mqd_control); in cik_cp_compute_resume()
5046 WREG32(CP_HQD_PQ_BASE, mqd->queue_state.cp_hqd_pq_base); in cik_cp_compute_resume()
5047 WREG32(CP_HQD_PQ_BASE_HI, mqd->queue_state.cp_hqd_pq_base_hi); in cik_cp_compute_resume()
5065 WREG32(CP_HQD_PQ_CONTROL, mqd->queue_state.cp_hqd_pq_control); in cik_cp_compute_resume()
5074 WREG32(CP_HQD_PQ_WPTR_POLL_ADDR, mqd->queue_state.cp_hqd_pq_wptr_poll_addr); in cik_cp_compute_resume()
5075 WREG32(CP_HQD_PQ_WPTR_POLL_ADDR_HI, in cik_cp_compute_resume()
5086 WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR, in cik_cp_compute_resume()
5088 WREG32(CP_HQD_PQ_RPTR_REPORT_ADDR_HI, in cik_cp_compute_resume()
5105 WREG32(CP_HQD_PQ_DOORBELL_CONTROL, in cik_cp_compute_resume()
5111 WREG32(CP_HQD_PQ_WPTR, mqd->queue_state.cp_hqd_pq_wptr); in cik_cp_compute_resume()
5116 WREG32(CP_HQD_VMID, mqd->queue_state.cp_hqd_vmid); in cik_cp_compute_resume()
5120 WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active); in cik_cp_compute_resume()
5339 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_soft_reset()
5342 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT); in cik_gpu_soft_reset()
5348 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()
5354 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_soft_reset()
5404 WREG32(GRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5410 WREG32(GRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5418 WREG32(SRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5424 WREG32(SRBM_SOFT_RESET, tmp); in cik_gpu_soft_reset()
5450 WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute & ~RENG_EXECUTE_ON_PWR_UP); in kv_save_regs_for_reset()
5451 WREG32(GMCON_MISC, save->gmcon_misc & ~(RENG_EXECUTE_ON_REG_UPDATE | in kv_save_regs_for_reset()
5460 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5461 WREG32(GMCON_PGFSM_CONFIG, 0x200010ff); in kv_restore_regs_for_reset()
5464 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5466 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5467 WREG32(GMCON_PGFSM_CONFIG, 0x300010ff); in kv_restore_regs_for_reset()
5470 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5472 WREG32(GMCON_PGFSM_WRITE, 0x210000); in kv_restore_regs_for_reset()
5473 WREG32(GMCON_PGFSM_CONFIG, 0xa00010ff); in kv_restore_regs_for_reset()
5476 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5478 WREG32(GMCON_PGFSM_WRITE, 0x21003); in kv_restore_regs_for_reset()
5479 WREG32(GMCON_PGFSM_CONFIG, 0xb00010ff); in kv_restore_regs_for_reset()
5482 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5484 WREG32(GMCON_PGFSM_WRITE, 0x2b00); in kv_restore_regs_for_reset()
5485 WREG32(GMCON_PGFSM_CONFIG, 0xc00010ff); in kv_restore_regs_for_reset()
5488 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5490 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5491 WREG32(GMCON_PGFSM_CONFIG, 0xd00010ff); in kv_restore_regs_for_reset()
5494 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5496 WREG32(GMCON_PGFSM_WRITE, 0x420000); in kv_restore_regs_for_reset()
5497 WREG32(GMCON_PGFSM_CONFIG, 0x100010ff); in kv_restore_regs_for_reset()
5500 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5502 WREG32(GMCON_PGFSM_WRITE, 0x120202); in kv_restore_regs_for_reset()
5503 WREG32(GMCON_PGFSM_CONFIG, 0x500010ff); in kv_restore_regs_for_reset()
5506 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5508 WREG32(GMCON_PGFSM_WRITE, 0x3e3e36); in kv_restore_regs_for_reset()
5509 WREG32(GMCON_PGFSM_CONFIG, 0x600010ff); in kv_restore_regs_for_reset()
5512 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5514 WREG32(GMCON_PGFSM_WRITE, 0x373f3e); in kv_restore_regs_for_reset()
5515 WREG32(GMCON_PGFSM_CONFIG, 0x700010ff); in kv_restore_regs_for_reset()
5518 WREG32(GMCON_PGFSM_WRITE, 0); in kv_restore_regs_for_reset()
5520 WREG32(GMCON_PGFSM_WRITE, 0x3e1332); in kv_restore_regs_for_reset()
5521 WREG32(GMCON_PGFSM_CONFIG, 0xe00010ff); in kv_restore_regs_for_reset()
5523 WREG32(GMCON_MISC3, save->gmcon_misc3); in kv_restore_regs_for_reset()
5524 WREG32(GMCON_MISC, save->gmcon_misc); in kv_restore_regs_for_reset()
5525 WREG32(GMCON_RENG_EXECUTE, save->gmcon_reng_execute); in kv_restore_regs_for_reset()
5543 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_pci_config_reset()
5546 WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT); in cik_gpu_pci_config_reset()
5551 WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
5555 WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_gpu_pci_config_reset()
5665 WREG32((0x2c14 + j), 0x00000000); in cik_mc_program()
5666 WREG32((0x2c18 + j), 0x00000000); in cik_mc_program()
5667 WREG32((0x2c1c + j), 0x00000000); in cik_mc_program()
5668 WREG32((0x2c20 + j), 0x00000000); in cik_mc_program()
5669 WREG32((0x2c24 + j), 0x00000000); in cik_mc_program()
5671 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); in cik_mc_program()
5678 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); in cik_mc_program()
5680 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in cik_mc_program()
5682 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in cik_mc_program()
5684 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, in cik_mc_program()
5688 WREG32(MC_VM_FB_LOCATION, tmp); in cik_mc_program()
5690 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in cik_mc_program()
5691 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); in cik_mc_program()
5692 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); in cik_mc_program()
5693 WREG32(MC_VM_AGP_BASE, 0); in cik_mc_program()
5694 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); in cik_mc_program()
5695 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); in cik_mc_program()
5788 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0); in cik_pcie_gart_tlb_flush()
5791 WREG32(VM_INVALIDATE_REQUEST, 0x1); in cik_pcie_gart_tlb_flush()
5807 WREG32(SH_MEM_CONFIG, sh_mem_config); in cik_pcie_init_compute_vmid()
5808 WREG32(SH_MEM_APE1_BASE, 1); in cik_pcie_init_compute_vmid()
5809 WREG32(SH_MEM_APE1_LIMIT, 0); in cik_pcie_init_compute_vmid()
5810 WREG32(SH_MEM_BASES, sh_mem_bases); in cik_pcie_init_compute_vmid()
5839 WREG32(MC_VM_MX_L1_TLB_CNTL, in cik_pcie_gart_enable()
5847 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in cik_pcie_gart_enable()
5853 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in cik_pcie_gart_enable()
5854 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cik_pcie_gart_enable()
5858 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in cik_pcie_gart_enable()
5859 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in cik_pcie_gart_enable()
5860 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in cik_pcie_gart_enable()
5861 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, in cik_pcie_gart_enable()
5863 WREG32(VM_CONTEXT0_CNTL2, 0); in cik_pcie_gart_enable()
5864 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in cik_pcie_gart_enable()
5867 WREG32(0x15D4, 0); in cik_pcie_gart_enable()
5868 WREG32(0x15D8, 0); in cik_pcie_gart_enable()
5869 WREG32(0x15DC, 0); in cik_pcie_gart_enable()
5873 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); in cik_pcie_gart_enable()
5874 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1); in cik_pcie_gart_enable()
5877 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), in cik_pcie_gart_enable()
5880 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), in cik_pcie_gart_enable()
5885 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, in cik_pcie_gart_enable()
5887 WREG32(VM_CONTEXT1_CNTL2, 4); in cik_pcie_gart_enable()
5888 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in cik_pcie_gart_enable()
5906 WREG32(CHUB_CONTROL, tmp); in cik_pcie_gart_enable()
5915 WREG32(SH_MEM_CONFIG, 0); in cik_pcie_gart_enable()
5916 WREG32(SH_MEM_APE1_BASE, 1); in cik_pcie_gart_enable()
5917 WREG32(SH_MEM_APE1_LIMIT, 0); in cik_pcie_gart_enable()
5918 WREG32(SH_MEM_BASES, 0); in cik_pcie_gart_enable()
5920 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5921 WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5922 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA1_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5923 WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0); in cik_pcie_gart_enable()
5960 WREG32(VM_CONTEXT0_CNTL, 0); in cik_pcie_gart_disable()
5961 WREG32(VM_CONTEXT1_CNTL, 0); in cik_pcie_gart_disable()
5963 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS | in cik_pcie_gart_disable()
5966 WREG32(VM_L2_CNTL, in cik_pcie_gart_disable()
5972 WREG32(VM_L2_CNTL2, 0); in cik_pcie_gart_disable()
5973 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in cik_pcie_gart_disable()
6178 WREG32(CP_INT_CNTL_RING0, tmp); in cik_enable_gui_idle_interrupt()
6190 WREG32(RLC_LB_CNTL, tmp); in cik_enable_lbpw()
6226 WREG32(RLC_CNTL, rlc); in cik_update_rlc()
6239 WREG32(RLC_CNTL, data); in cik_halt_rlc()
6258 WREG32(RLC_GPR_REG2, tmp); in cik_enter_rlc_safe_mode()
6279 WREG32(RLC_GPR_REG2, tmp); in cik_exit_rlc_safe_mode()
6291 WREG32(RLC_CNTL, 0); in cik_rlc_stop()
6307 WREG32(RLC_CNTL, RLC_ENABLE); in cik_rlc_start()
6334 WREG32(RLC_CGCG_CGLS_CTRL, tmp); in cik_rlc_resume()
6342 WREG32(RLC_LB_CNTR_INIT, 0); in cik_rlc_resume()
6343 WREG32(RLC_LB_CNTR_MAX, 0x00008000); in cik_rlc_resume()
6347 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff); in cik_rlc_resume()
6348 WREG32(RLC_LB_PARAMS, 0x00600408); in cik_rlc_resume()
6349 WREG32(RLC_LB_CNTL, 0x80000004); in cik_rlc_resume()
6352 WREG32(RLC_MC_CNTL, 0); in cik_rlc_resume()
6353 WREG32(RLC_UCODE_CNTL, 0); in cik_rlc_resume()
6364 WREG32(RLC_GPM_UCODE_ADDR, 0); in cik_rlc_resume()
6366 WREG32(RLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++)); in cik_rlc_resume()
6367 WREG32(RLC_GPM_UCODE_ADDR, le32_to_cpu(hdr->header.ucode_version)); in cik_rlc_resume()
6389 WREG32(RLC_GPM_UCODE_ADDR, 0); in cik_rlc_resume()
6391 WREG32(RLC_GPM_UCODE_DATA, be32_to_cpup(fw_data++)); in cik_rlc_resume()
6392 WREG32(RLC_GPM_UCODE_ADDR, 0); in cik_rlc_resume()
6399 WREG32(RLC_DRIVER_DMA_STATUS, 0); in cik_rlc_resume()
6419 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in cik_enable_cgcg()
6420 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in cik_enable_cgcg()
6422 WREG32(RLC_SERDES_WR_CTRL, tmp2); in cik_enable_cgcg()
6440 WREG32(RLC_CGCG_CGLS_CTRL, data); in cik_enable_cgcg()
6454 WREG32(CP_MEM_SLP_CNTL, data); in cik_enable_mgcg()
6462 WREG32(RLC_CGTT_MGCG_OVERRIDE, data); in cik_enable_mgcg()
6468 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in cik_enable_mgcg()
6469 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in cik_enable_mgcg()
6471 WREG32(RLC_SERDES_WR_CTRL, data); in cik_enable_mgcg()
6489 WREG32(CGTS_SM_CTRL_REG, data); in cik_enable_mgcg()
6495 WREG32(RLC_CGTT_MGCG_OVERRIDE, data); in cik_enable_mgcg()
6500 WREG32(RLC_MEM_SLP_CNTL, data); in cik_enable_mgcg()
6506 WREG32(CP_MEM_SLP_CNTL, data); in cik_enable_mgcg()
6512 WREG32(CGTS_SM_CTRL_REG, data); in cik_enable_mgcg()
6518 WREG32(RLC_SERDES_WR_CU_MASTER_MASK, 0xffffffff); in cik_enable_mgcg()
6519 WREG32(RLC_SERDES_WR_NONCU_MASTER_MASK, 0xffffffff); in cik_enable_mgcg()
6521 WREG32(RLC_SERDES_WR_CTRL, data); in cik_enable_mgcg()
6554 WREG32(mc_cg_registers[i], data); in cik_enable_mc_ls()
6571 WREG32(mc_cg_registers[i], data); in cik_enable_mc_mgcg()
6581 WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
6582 WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, 0x00000100); in cik_enable_sdma_mgcg()
6587 WREG32(SDMA0_CLK_CTRL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
6592 WREG32(SDMA0_CLK_CTRL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgcg()
6605 WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6610 WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6615 WREG32(SDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6620 WREG32(SDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); in cik_enable_sdma_mgls()
6637 WREG32(UVD_CGC_CTRL, data); in cik_enable_uvd_mgcg()
6646 WREG32(UVD_CGC_CTRL, data); in cik_enable_uvd_mgcg()
6681 WREG32(HDP_HOST_PATH_CNTL, data); in cik_enable_hdp_mgcg()
6697 WREG32(HDP_MEM_POWER_LS, data); in cik_enable_hdp_ls()
6785 WREG32(RLC_PG_CNTL, data); in cik_enable_sck_slowdown_on_pu()
6799 WREG32(RLC_PG_CNTL, data); in cik_enable_sck_slowdown_on_pd()
6812 WREG32(RLC_PG_CNTL, data); in cik_enable_cp_pg()
6825 WREG32(RLC_PG_CNTL, data); in cik_enable_gds_pg()
6925 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_cgpg()
6930 WREG32(RLC_AUTO_PG_CTRL, data); in cik_enable_gfx_cgpg()
6935 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_cgpg()
6940 WREG32(RLC_AUTO_PG_CTRL, data); in cik_enable_gfx_cgpg()
6996 WREG32(RLC_PG_AO_CU_MASK, tmp); in cik_init_ao_cu_mask()
7001 WREG32(RLC_MAX_PG_CU, tmp); in cik_init_ao_cu_mask()
7015 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_static_mgpg()
7029 WREG32(RLC_PG_CNTL, data); in cik_enable_gfx_dynamic_mgpg()
7041 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); in cik_init_gfx_cgpg()
7042 WREG32(RLC_GPM_SCRATCH_DATA, upper_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
7043 WREG32(RLC_GPM_SCRATCH_DATA, lower_32_bits(rdev->rlc.clear_state_gpu_addr)); in cik_init_gfx_cgpg()
7044 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.clear_state_size); in cik_init_gfx_cgpg()
7046 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_CLEAR_STATE_DESCRIPTOR_OFFSET); in cik_init_gfx_cgpg()
7048 WREG32(RLC_GPM_SCRATCH_DATA, 0); in cik_init_gfx_cgpg()
7051 WREG32(RLC_GPM_SCRATCH_ADDR, RLC_SAVE_AND_RESTORE_STARTING_OFFSET); in cik_init_gfx_cgpg()
7053 WREG32(RLC_GPM_SCRATCH_DATA, rdev->rlc.reg_list[i]); in cik_init_gfx_cgpg()
7059 WREG32(RLC_PG_CNTL, data); in cik_init_gfx_cgpg()
7061 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in cik_init_gfx_cgpg()
7062 WREG32(RLC_CP_TABLE_RESTORE, rdev->rlc.cp_table_gpu_addr >> 8); in cik_init_gfx_cgpg()
7067 WREG32(CP_RB_WPTR_POLL_CNTL, data); in cik_init_gfx_cgpg()
7070 WREG32(RLC_PG_DELAY, data); in cik_init_gfx_cgpg()
7075 WREG32(RLC_PG_DELAY_2, data); in cik_init_gfx_cgpg()
7080 WREG32(RLC_AUTO_PG_CTRL, data); in cik_init_gfx_cgpg()
7243 WREG32(IH_CNTL, ih_cntl); in cik_enable_interrupts()
7244 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_enable_interrupts()
7262 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_disable_interrupts()
7263 WREG32(IH_CNTL, ih_cntl); in cik_disable_interrupts()
7265 WREG32(IH_RB_RPTR, 0); in cik_disable_interrupts()
7266 WREG32(IH_RB_WPTR, 0); in cik_disable_interrupts()
7285 WREG32(CP_INT_CNTL_RING0, tmp); in cik_disable_interrupt_state()
7288 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state()
7290 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp); in cik_disable_interrupt_state()
7292 WREG32(CP_ME1_PIPE0_INT_CNTL, 0); in cik_disable_interrupt_state()
7293 WREG32(CP_ME1_PIPE1_INT_CNTL, 0); in cik_disable_interrupt_state()
7294 WREG32(CP_ME1_PIPE2_INT_CNTL, 0); in cik_disable_interrupt_state()
7295 WREG32(CP_ME1_PIPE3_INT_CNTL, 0); in cik_disable_interrupt_state()
7296 WREG32(CP_ME2_PIPE0_INT_CNTL, 0); in cik_disable_interrupt_state()
7297 WREG32(CP_ME2_PIPE1_INT_CNTL, 0); in cik_disable_interrupt_state()
7298 WREG32(CP_ME2_PIPE2_INT_CNTL, 0); in cik_disable_interrupt_state()
7299 WREG32(CP_ME2_PIPE3_INT_CNTL, 0); in cik_disable_interrupt_state()
7301 WREG32(GRBM_INT_CNTL, 0); in cik_disable_interrupt_state()
7303 WREG32(SRBM_INT_CNTL, 0); in cik_disable_interrupt_state()
7305 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7306 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7308 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7309 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7312 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7313 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7317 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7318 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7321 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7322 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7325 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7326 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()
7330 WREG32(DAC_AUTODETECT_INT_CONTROL, 0); in cik_disable_interrupt_state()
7334 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_disable_interrupt_state()
7336 WREG32(DC_HPD2_INT_CONTROL, tmp); in cik_disable_interrupt_state()
7338 WREG32(DC_HPD3_INT_CONTROL, tmp); in cik_disable_interrupt_state()
7340 WREG32(DC_HPD4_INT_CONTROL, tmp); in cik_disable_interrupt_state()
7342 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_disable_interrupt_state()
7344 WREG32(DC_HPD6_INT_CONTROL, tmp); in cik_disable_interrupt_state()
7382 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); in cik_irq_init()
7390 WREG32(INTERRUPT_CNTL, interrupt_cntl); in cik_irq_init()
7392 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); in cik_irq_init()
7403 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); in cik_irq_init()
7404 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); in cik_irq_init()
7406 WREG32(IH_RB_CNTL, ih_rb_cntl); in cik_irq_init()
7409 WREG32(IH_RB_RPTR, 0); in cik_irq_init()
7410 WREG32(IH_RB_WPTR, 0); in cik_irq_init()
7417 WREG32(IH_CNTL, ih_cntl); in cik_irq_init()
7579 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in cik_irq_set()
7581 WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl); in cik_irq_set()
7582 WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1); in cik_irq_set()
7584 WREG32(CP_ME1_PIPE0_INT_CNTL, cp_m1p0); in cik_irq_set()
7586 WREG32(GRBM_INT_CNTL, grbm_int_cntl); in cik_irq_set()
7588 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); in cik_irq_set()
7589 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); in cik_irq_set()
7591 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); in cik_irq_set()
7592 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); in cik_irq_set()
7595 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); in cik_irq_set()
7596 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); in cik_irq_set()
7600 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, in cik_irq_set()
7602 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, in cik_irq_set()
7606 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, in cik_irq_set()
7608 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, in cik_irq_set()
7612 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, in cik_irq_set()
7614 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, in cik_irq_set()
7618 WREG32(DC_HPD1_INT_CONTROL, hpd1); in cik_irq_set()
7619 WREG32(DC_HPD2_INT_CONTROL, hpd2); in cik_irq_set()
7620 WREG32(DC_HPD3_INT_CONTROL, hpd3); in cik_irq_set()
7621 WREG32(DC_HPD4_INT_CONTROL, hpd4); in cik_irq_set()
7622 WREG32(DC_HPD5_INT_CONTROL, hpd5); in cik_irq_set()
7623 WREG32(DC_HPD6_INT_CONTROL, hpd6); in cik_irq_set()
7670 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, in cik_irq_ack()
7673 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, in cik_irq_ack()
7676 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7678 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7680 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7682 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7686 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, in cik_irq_ack()
7689 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, in cik_irq_ack()
7692 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7694 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7696 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7698 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7703 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, in cik_irq_ack()
7706 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, in cik_irq_ack()
7709 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7711 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7713 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()
7715 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
7721 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_irq_ack()
7726 WREG32(DC_HPD2_INT_CONTROL, tmp); in cik_irq_ack()
7731 WREG32(DC_HPD3_INT_CONTROL, tmp); in cik_irq_ack()
7736 WREG32(DC_HPD4_INT_CONTROL, tmp); in cik_irq_ack()
7741 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_irq_ack()
7746 WREG32(DC_HPD6_INT_CONTROL, tmp); in cik_irq_ack()
7751 WREG32(DC_HPD1_INT_CONTROL, tmp); in cik_irq_ack()
7756 WREG32(DC_HPD2_INT_CONTROL, tmp); in cik_irq_ack()
7761 WREG32(DC_HPD3_INT_CONTROL, tmp); in cik_irq_ack()
7766 WREG32(DC_HPD4_INT_CONTROL, tmp); in cik_irq_ack()
7771 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_irq_ack()
7776 WREG32(DC_HPD6_INT_CONTROL, tmp); in cik_irq_ack()
7856 WREG32(IH_RB_CNTL, tmp); in cik_get_ih_wptr()
8246 WREG32(SRBM_INT_ACK, 0x1); in cik_irq_process()
8445 WREG32(IH_RB_RPTR, rptr); in cik_irq_process()
9056 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_fmt()
9106 WREG32(LB_MEMORY_CTRL + radeon_crtc->crtc_offset, in dce8_line_buffer_adjust()
9109 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce8_line_buffer_adjust()
9615 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_watermarks()
9616 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce8_program_watermarks()
9623 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_watermarks()
9624 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce8_program_watermarks()
9628 WREG32(DPG_WATERMARK_MASK_CONTROL + radeon_crtc->crtc_offset, wm_mask); in dce8_program_watermarks()
9679 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); in cik_get_gpu_clock_counter()