Lines Matching refs:gb_tile_moden
2323 u32 reg_offset, gb_tile_moden, split_equal_to_row_size; in cik_tiling_mode_table_init() local
2349 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2355 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2361 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2367 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2373 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2379 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2384 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2390 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2396 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in cik_tiling_mode_table_init()
2400 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2405 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2411 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
2417 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2423 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2428 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2434 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
2440 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2446 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2451 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2457 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
2463 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2469 gb_tile_moden = 0; in cik_tiling_mode_table_init()
2472 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()
2473 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
2478 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2484 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2490 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2496 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2502 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2508 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2514 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2520 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2526 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2532 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2538 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2544 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2550 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2556 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2562 gb_tile_moden = 0; in cik_tiling_mode_table_init()
2565 rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()
2566 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
2572 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2578 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2584 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2590 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2596 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2602 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2607 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2613 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2619 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in cik_tiling_mode_table_init()
2623 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2628 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2634 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
2640 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2646 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2651 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2657 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
2663 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2669 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2674 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2680 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
2686 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2692 gb_tile_moden = 0; in cik_tiling_mode_table_init()
2695 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()
2696 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
2701 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2707 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2713 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2719 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2725 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2731 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2737 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2743 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2749 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2755 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2761 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2767 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2773 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2779 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
2785 gb_tile_moden = 0; in cik_tiling_mode_table_init()
2788 rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()
2789 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
2796 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2802 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2808 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2814 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2820 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2826 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2831 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2837 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2843 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in cik_tiling_mode_table_init()
2847 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2852 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2858 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
2864 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2870 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2875 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2881 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
2887 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2893 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2898 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2904 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
2910 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2916 gb_tile_moden = 0; in cik_tiling_mode_table_init()
2919 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()
2920 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
2926 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2932 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2938 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2944 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2950 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2956 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2961 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2967 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2973 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in cik_tiling_mode_table_init()
2977 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
2982 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
2988 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
2994 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3000 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
3005 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3011 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
3017 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3023 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
3028 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3034 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
3040 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3046 gb_tile_moden = 0; in cik_tiling_mode_table_init()
3049 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()
3050 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
3056 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3062 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3068 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3074 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3080 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3086 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3092 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3098 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
3104 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
3110 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3116 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3122 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3128 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3134 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3140 gb_tile_moden = 0; in cik_tiling_mode_table_init()
3143 rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()
3144 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
3150 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3156 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3162 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3168 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3174 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3180 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
3185 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3191 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3197 gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) | in cik_tiling_mode_table_init()
3201 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
3206 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3212 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
3218 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3224 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
3229 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3235 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
3241 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3247 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) | in cik_tiling_mode_table_init()
3252 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3258 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) | in cik_tiling_mode_table_init()
3264 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) | in cik_tiling_mode_table_init()
3270 gb_tile_moden = 0; in cik_tiling_mode_table_init()
3273 rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()
3274 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()
3279 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
3285 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
3291 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3297 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3303 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3309 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3315 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3321 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in cik_tiling_mode_table_init()
3327 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) | in cik_tiling_mode_table_init()
3333 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
3339 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in cik_tiling_mode_table_init()
3345 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3351 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3357 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in cik_tiling_mode_table_init()
3363 gb_tile_moden = 0; in cik_tiling_mode_table_init()
3366 rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden; in cik_tiling_mode_table_init()
3367 WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden); in cik_tiling_mode_table_init()