Lines Matching refs:tmp
1226 u32 tmp = 0; in dce4_program_fmt() local
1251 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE | in dce4_program_fmt()
1254 tmp |= FMT_TRUNCATE_EN; in dce4_program_fmt()
1259 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE | in dce4_program_fmt()
1263 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); in dce4_program_fmt()
1271 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce4_program_fmt()
1347 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset); in evergreen_page_flip() local
1351 tmp |= EVERGREEN_GRPH_UPDATE_LOCK; in evergreen_page_flip()
1352 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in evergreen_page_flip()
1374 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK; in evergreen_page_flip()
1375 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp); in evergreen_page_flip()
1620 u32 tmp; in evergreen_pm_prepare() local
1626 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); in evergreen_pm_prepare()
1627 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; in evergreen_pm_prepare()
1628 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in evergreen_pm_prepare()
1645 u32 tmp; in evergreen_pm_finish() local
1651 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); in evergreen_pm_finish()
1652 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; in evergreen_pm_finish()
1653 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp); in evergreen_pm_finish()
1714 u32 tmp; in evergreen_hpd_set_polarity() local
1719 tmp = RREG32(DC_HPD1_INT_CONTROL); in evergreen_hpd_set_polarity()
1721 tmp &= ~DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1723 tmp |= DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1724 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1727 tmp = RREG32(DC_HPD2_INT_CONTROL); in evergreen_hpd_set_polarity()
1729 tmp &= ~DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1731 tmp |= DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1732 WREG32(DC_HPD2_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1735 tmp = RREG32(DC_HPD3_INT_CONTROL); in evergreen_hpd_set_polarity()
1737 tmp &= ~DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1739 tmp |= DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1740 WREG32(DC_HPD3_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1743 tmp = RREG32(DC_HPD4_INT_CONTROL); in evergreen_hpd_set_polarity()
1745 tmp &= ~DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1747 tmp |= DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1748 WREG32(DC_HPD4_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1751 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_hpd_set_polarity()
1753 tmp &= ~DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1755 tmp |= DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1756 WREG32(DC_HPD5_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1759 tmp = RREG32(DC_HPD6_INT_CONTROL); in evergreen_hpd_set_polarity()
1761 tmp &= ~DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1763 tmp |= DC_HPDx_INT_POLARITY; in evergreen_hpd_set_polarity()
1764 WREG32(DC_HPD6_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
1784 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | in evergreen_hpd_init() local
1801 WREG32(DC_HPD1_CONTROL, tmp); in evergreen_hpd_init()
1804 WREG32(DC_HPD2_CONTROL, tmp); in evergreen_hpd_init()
1807 WREG32(DC_HPD3_CONTROL, tmp); in evergreen_hpd_init()
1810 WREG32(DC_HPD4_CONTROL, tmp); in evergreen_hpd_init()
1813 WREG32(DC_HPD5_CONTROL, tmp); in evergreen_hpd_init()
1816 WREG32(DC_HPD6_CONTROL, tmp); in evergreen_hpd_init()
1877 u32 tmp, buffer_alloc, i; in evergreen_line_buffer_adjust() local
1902 tmp = 0; /* 1/2 */ in evergreen_line_buffer_adjust()
1905 tmp = 2; /* whole */ in evergreen_line_buffer_adjust()
1909 tmp = 0; in evergreen_line_buffer_adjust()
1915 tmp += 4; in evergreen_line_buffer_adjust()
1916 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp); in evergreen_line_buffer_adjust()
1930 switch (tmp) { in evergreen_line_buffer_adjust()
1965 u32 tmp = RREG32(MC_SHARED_CHMAP); in evergreen_get_number_of_dram_channels() local
1967 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { in evergreen_get_number_of_dram_channels()
2221 u32 tmp, arb_control3; in evergreen_program_watermarks() local
2334 tmp = arb_control3; in evergreen_program_watermarks()
2335 tmp &= ~LATENCY_WATERMARK_MASK(3); in evergreen_program_watermarks()
2336 tmp |= LATENCY_WATERMARK_MASK(1); in evergreen_program_watermarks()
2337 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); in evergreen_program_watermarks()
2342 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); in evergreen_program_watermarks()
2343 tmp &= ~LATENCY_WATERMARK_MASK(3); in evergreen_program_watermarks()
2344 tmp |= LATENCY_WATERMARK_MASK(2); in evergreen_program_watermarks()
2345 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp); in evergreen_program_watermarks()
2408 u32 tmp; in evergreen_mc_wait_for_idle() local
2412 tmp = RREG32(SRBM_STATUS) & 0x1F00; in evergreen_mc_wait_for_idle()
2413 if (!tmp) in evergreen_mc_wait_for_idle()
2426 u32 tmp; in evergreen_pcie_gart_tlb_flush() local
2433 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); in evergreen_pcie_gart_tlb_flush()
2434 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; in evergreen_pcie_gart_tlb_flush()
2435 if (tmp == 2) { in evergreen_pcie_gart_tlb_flush()
2439 if (tmp) { in evergreen_pcie_gart_tlb_flush()
2448 u32 tmp; in evergreen_pcie_gart_enable() local
2465 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in evergreen_pcie_gart_enable()
2470 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_enable()
2471 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_enable()
2472 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_enable()
2474 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_enable()
2475 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_enable()
2476 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_enable()
2481 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp); in evergreen_pcie_gart_enable()
2483 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_enable()
2484 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_enable()
2485 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_enable()
2486 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); in evergreen_pcie_gart_enable()
2506 u32 tmp; in evergreen_pcie_gart_disable() local
2518 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); in evergreen_pcie_gart_disable()
2519 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_disable()
2520 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_disable()
2521 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_disable()
2522 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); in evergreen_pcie_gart_disable()
2523 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); in evergreen_pcie_gart_disable()
2524 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); in evergreen_pcie_gart_disable()
2525 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); in evergreen_pcie_gart_disable()
2539 u32 tmp; in evergreen_agp_enable() local
2548 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in evergreen_agp_enable()
2552 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); in evergreen_agp_enable()
2553 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); in evergreen_agp_enable()
2554 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); in evergreen_agp_enable()
2555 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); in evergreen_agp_enable()
2556 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); in evergreen_agp_enable()
2557 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); in evergreen_agp_enable()
2558 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); in evergreen_agp_enable()
2706 u32 crtc_enabled, tmp, frame_count, blackout; in evergreen_mc_stop() local
2723 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()
2724 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) { in evergreen_mc_stop()
2727 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN; in evergreen_mc_stop()
2728 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()
2732 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()
2733 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) { in evergreen_mc_stop()
2736 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; in evergreen_mc_stop()
2737 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()
2761 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()
2762 tmp &= ~EVERGREEN_CRTC_MASTER_EN; in evergreen_mc_stop()
2763 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()
2788 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in evergreen_mc_stop()
2789 if (!(tmp & EVERGREEN_GRPH_UPDATE_LOCK)) { in evergreen_mc_stop()
2790 tmp |= EVERGREEN_GRPH_UPDATE_LOCK; in evergreen_mc_stop()
2791 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); in evergreen_mc_stop()
2793 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); in evergreen_mc_stop()
2794 if (!(tmp & 1)) { in evergreen_mc_stop()
2795 tmp |= 1; in evergreen_mc_stop()
2796 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); in evergreen_mc_stop()
2804 u32 tmp, frame_count; in evergreen_mc_resume() local
2827 tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]); in evergreen_mc_resume()
2828 if ((tmp & 0x7) != 3) { in evergreen_mc_resume()
2829 tmp &= ~0x7; in evergreen_mc_resume()
2830 tmp |= 0x3; in evergreen_mc_resume()
2831 WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp); in evergreen_mc_resume()
2833 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in evergreen_mc_resume()
2834 if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) { in evergreen_mc_resume()
2835 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK; in evergreen_mc_resume()
2836 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp); in evergreen_mc_resume()
2838 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); in evergreen_mc_resume()
2839 if (tmp & 1) { in evergreen_mc_resume()
2840 tmp &= ~1; in evergreen_mc_resume()
2841 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp); in evergreen_mc_resume()
2844 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in evergreen_mc_resume()
2845 if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0) in evergreen_mc_resume()
2853 tmp = RREG32(MC_SHARED_BLACKOUT_CNTL); in evergreen_mc_resume()
2854 tmp &= ~BLACKOUT_MODE_MASK; in evergreen_mc_resume()
2855 WREG32(MC_SHARED_BLACKOUT_CNTL, tmp); in evergreen_mc_resume()
2862 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); in evergreen_mc_resume()
2863 tmp &= ~EVERGREEN_CRTC_BLANK_DATA_EN; in evergreen_mc_resume()
2865 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_resume()
2868 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); in evergreen_mc_resume()
2869 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE; in evergreen_mc_resume()
2871 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_resume()
2894 u32 tmp; in evergreen_mc_program() local
2939 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF; in evergreen_mc_program()
2940 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24; in evergreen_mc_program()
2941 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20; in evergreen_mc_program()
2942 WREG32(MC_FUS_VM_FB_OFFSET, tmp); in evergreen_mc_program()
2944 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in evergreen_mc_program()
2945 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in evergreen_mc_program()
2946 WREG32(MC_VM_FB_LOCATION, tmp); in evergreen_mc_program()
3107 u32 tmp; in evergreen_cp_resume() local
3125 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in evergreen_cp_resume()
3127 tmp |= BUF_SWAP_32BIT; in evergreen_cp_resume()
3129 WREG32(CP_RB_CNTL, tmp); in evergreen_cp_resume()
3137 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); in evergreen_cp_resume()
3151 tmp |= RB_NO_UPDATE; in evergreen_cp_resume()
3156 WREG32(CP_RB_CNTL, tmp); in evergreen_cp_resume()
3191 u32 hdp_host_path_cntl, tmp; in evergreen_gpu_init() local
3499 tmp = (((efuse_straps_4 & 0xf) << 4) | in evergreen_gpu_init()
3502 tmp = 0; in evergreen_gpu_init()
3509 tmp <<= 4; in evergreen_gpu_init()
3510 tmp |= rb_disable_bitmap; in evergreen_gpu_init()
3514 disabled_rb_mask = tmp; in evergreen_gpu_init()
3515 tmp = 0; in evergreen_gpu_init()
3517 tmp |= (1 << i); in evergreen_gpu_init()
3519 if ((disabled_rb_mask & tmp) == tmp) { in evergreen_gpu_init()
3531 tmp <<= 16; in evergreen_gpu_init()
3532 tmp |= simd_disable_bitmap; in evergreen_gpu_init()
3534 rdev->config.evergreen.active_simds = hweight32(~tmp); in evergreen_gpu_init()
3551 tmp = 0x11111111; in evergreen_gpu_init()
3554 tmp = 0x00000000; in evergreen_gpu_init()
3557 tmp = gb_addr_config & NUM_PIPES_MASK; in evergreen_gpu_init()
3558 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends, in evergreen_gpu_init()
3561 WREG32(GB_BACKEND_MAP, tmp); in evergreen_gpu_init()
3737 tmp = RREG32(HDP_MISC_CNTL); in evergreen_gpu_init()
3738 tmp |= HDP_FLUSH_INVALIDATE_CACHE; in evergreen_gpu_init()
3739 WREG32(HDP_MISC_CNTL, tmp); in evergreen_gpu_init()
3752 u32 tmp; in evergreen_mc_init() local
3760 tmp = RREG32(FUS_MC_ARB_RAMCFG); in evergreen_mc_init()
3762 tmp = RREG32(MC_ARB_RAMCFG); in evergreen_mc_init()
3763 if (tmp & CHANSIZE_OVERRIDE) { in evergreen_mc_init()
3765 } else if (tmp & CHANSIZE_MASK) { in evergreen_mc_init()
3770 tmp = RREG32(MC_SHARED_CHMAP); in evergreen_mc_init()
3771 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { in evergreen_mc_init()
3841 u32 i, j, tmp; in evergreen_is_display_hung() local
3853 tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in evergreen_is_display_hung()
3854 if (tmp != crtc_status[i]) in evergreen_is_display_hung()
3869 u32 tmp; in evergreen_gpu_check_soft_reset() local
3872 tmp = RREG32(GRBM_STATUS); in evergreen_gpu_check_soft_reset()
3873 if (tmp & (PA_BUSY | SC_BUSY | in evergreen_gpu_check_soft_reset()
3880 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING | in evergreen_gpu_check_soft_reset()
3884 if (tmp & GRBM_EE_BUSY) in evergreen_gpu_check_soft_reset()
3888 tmp = RREG32(DMA_STATUS_REG); in evergreen_gpu_check_soft_reset()
3889 if (!(tmp & DMA_IDLE)) in evergreen_gpu_check_soft_reset()
3893 tmp = RREG32(SRBM_STATUS2); in evergreen_gpu_check_soft_reset()
3894 if (tmp & DMA_BUSY) in evergreen_gpu_check_soft_reset()
3898 tmp = RREG32(SRBM_STATUS); in evergreen_gpu_check_soft_reset()
3899 if (tmp & (RLC_RQ_PENDING | RLC_BUSY)) in evergreen_gpu_check_soft_reset()
3902 if (tmp & IH_BUSY) in evergreen_gpu_check_soft_reset()
3905 if (tmp & SEM_BUSY) in evergreen_gpu_check_soft_reset()
3908 if (tmp & GRBM_RQ_PENDING) in evergreen_gpu_check_soft_reset()
3911 if (tmp & VMC_BUSY) in evergreen_gpu_check_soft_reset()
3914 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY | in evergreen_gpu_check_soft_reset()
3922 tmp = RREG32(VM_L2_STATUS); in evergreen_gpu_check_soft_reset()
3923 if (tmp & L2_BUSY) in evergreen_gpu_check_soft_reset()
3939 u32 tmp; in evergreen_gpu_soft_reset() local
3953 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_soft_reset()
3954 tmp &= ~DMA_RB_ENABLE; in evergreen_gpu_soft_reset()
3955 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_soft_reset()
4013 tmp = RREG32(GRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4014 tmp |= grbm_soft_reset; in evergreen_gpu_soft_reset()
4015 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in evergreen_gpu_soft_reset()
4016 WREG32(GRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
4017 tmp = RREG32(GRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4021 tmp &= ~grbm_soft_reset; in evergreen_gpu_soft_reset()
4022 WREG32(GRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
4023 tmp = RREG32(GRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4027 tmp = RREG32(SRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4028 tmp |= srbm_soft_reset; in evergreen_gpu_soft_reset()
4029 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in evergreen_gpu_soft_reset()
4030 WREG32(SRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
4031 tmp = RREG32(SRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4035 tmp &= ~srbm_soft_reset; in evergreen_gpu_soft_reset()
4036 WREG32(SRBM_SOFT_RESET, tmp); in evergreen_gpu_soft_reset()
4037 tmp = RREG32(SRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4052 u32 tmp, i; in evergreen_gpu_pci_config_reset() local
4062 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_pci_config_reset()
4063 tmp &= ~DMA_RB_ENABLE; in evergreen_gpu_pci_config_reset()
4064 WREG32(DMA_RB_CNTL, tmp); in evergreen_gpu_pci_config_reset()
4433 u32 tmp = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; in evergreen_rlc_resume() local
4434 tmp |= 0xffffffff << rdev->config.cayman.max_simds_per_se; in evergreen_rlc_resume()
4435 tmp = hweight32(~tmp); in evergreen_rlc_resume()
4436 if (tmp == rdev->config.cayman.max_simds_per_se) { in evergreen_rlc_resume()
4495 u32 tmp; in evergreen_disable_interrupt_state() local
4502 tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE; in evergreen_disable_interrupt_state()
4503 WREG32(CAYMAN_DMA1_CNTL, tmp); in evergreen_disable_interrupt_state()
4506 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_disable_interrupt_state()
4507 WREG32(DMA_CNTL, tmp); in evergreen_disable_interrupt_state()
4537 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4538 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4539 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4540 WREG32(DC_HPD2_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4541 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4542 WREG32(DC_HPD3_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4543 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4544 WREG32(DC_HPD4_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4545 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4546 WREG32(DC_HPD5_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4547 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4548 WREG32(DC_HPD6_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4784 u32 tmp; in evergreen_irq_ack() local
4854 tmp = RREG32(DC_HPD1_INT_CONTROL); in evergreen_irq_ack()
4855 tmp |= DC_HPDx_INT_ACK; in evergreen_irq_ack()
4856 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_irq_ack()
4859 tmp = RREG32(DC_HPD2_INT_CONTROL); in evergreen_irq_ack()
4860 tmp |= DC_HPDx_INT_ACK; in evergreen_irq_ack()
4861 WREG32(DC_HPD2_INT_CONTROL, tmp); in evergreen_irq_ack()
4864 tmp = RREG32(DC_HPD3_INT_CONTROL); in evergreen_irq_ack()
4865 tmp |= DC_HPDx_INT_ACK; in evergreen_irq_ack()
4866 WREG32(DC_HPD3_INT_CONTROL, tmp); in evergreen_irq_ack()
4869 tmp = RREG32(DC_HPD4_INT_CONTROL); in evergreen_irq_ack()
4870 tmp |= DC_HPDx_INT_ACK; in evergreen_irq_ack()
4871 WREG32(DC_HPD4_INT_CONTROL, tmp); in evergreen_irq_ack()
4874 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_irq_ack()
4875 tmp |= DC_HPDx_INT_ACK; in evergreen_irq_ack()
4876 WREG32(DC_HPD5_INT_CONTROL, tmp); in evergreen_irq_ack()
4879 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_irq_ack()
4880 tmp |= DC_HPDx_INT_ACK; in evergreen_irq_ack()
4881 WREG32(DC_HPD6_INT_CONTROL, tmp); in evergreen_irq_ack()
4885 tmp = RREG32(DC_HPD1_INT_CONTROL); in evergreen_irq_ack()
4886 tmp |= DC_HPDx_RX_INT_ACK; in evergreen_irq_ack()
4887 WREG32(DC_HPD1_INT_CONTROL, tmp); in evergreen_irq_ack()
4890 tmp = RREG32(DC_HPD2_INT_CONTROL); in evergreen_irq_ack()
4891 tmp |= DC_HPDx_RX_INT_ACK; in evergreen_irq_ack()
4892 WREG32(DC_HPD2_INT_CONTROL, tmp); in evergreen_irq_ack()
4895 tmp = RREG32(DC_HPD3_INT_CONTROL); in evergreen_irq_ack()
4896 tmp |= DC_HPDx_RX_INT_ACK; in evergreen_irq_ack()
4897 WREG32(DC_HPD3_INT_CONTROL, tmp); in evergreen_irq_ack()
4900 tmp = RREG32(DC_HPD4_INT_CONTROL); in evergreen_irq_ack()
4901 tmp |= DC_HPDx_RX_INT_ACK; in evergreen_irq_ack()
4902 WREG32(DC_HPD4_INT_CONTROL, tmp); in evergreen_irq_ack()
4905 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_irq_ack()
4906 tmp |= DC_HPDx_RX_INT_ACK; in evergreen_irq_ack()
4907 WREG32(DC_HPD5_INT_CONTROL, tmp); in evergreen_irq_ack()
4910 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_irq_ack()
4911 tmp |= DC_HPDx_RX_INT_ACK; in evergreen_irq_ack()
4912 WREG32(DC_HPD6_INT_CONTROL, tmp); in evergreen_irq_ack()
4916 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); in evergreen_irq_ack()
4917 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; in evergreen_irq_ack()
4918 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4921 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); in evergreen_irq_ack()
4922 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; in evergreen_irq_ack()
4923 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4926 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); in evergreen_irq_ack()
4927 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; in evergreen_irq_ack()
4928 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4931 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); in evergreen_irq_ack()
4932 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; in evergreen_irq_ack()
4933 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4936 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); in evergreen_irq_ack()
4937 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; in evergreen_irq_ack()
4938 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4941 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); in evergreen_irq_ack()
4942 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; in evergreen_irq_ack()
4943 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp); in evergreen_irq_ack()
4964 u32 wptr, tmp; in evergreen_get_ih_wptr() local
4980 tmp = RREG32(IH_RB_CNTL); in evergreen_get_ih_wptr()
4981 tmp |= IH_WPTR_OVERFLOW_CLEAR; in evergreen_get_ih_wptr()
4982 WREG32(IH_RB_CNTL, tmp); in evergreen_get_ih_wptr()