Lines Matching refs:RREG32
1030 *val = RREG32(reg); in evergreen_get_allowed_info_register()
1082 if (RREG32(status_reg) & DCLK_STATUS) in sumo_set_uvd_clock()
1095 u32 cg_scratch = RREG32(CG_SCRATCH1); in sumo_set_uvd_clocks()
1276 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK) in dce4_is_in_vblank()
1286 pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce4_is_counter_moving()
1287 pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce4_is_counter_moving()
1310 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN)) in dce4_wait_for_vblank()
1347 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset); in evergreen_page_flip()
1367 …if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDI… in evergreen_page_flip()
1391 return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & in evergreen_page_flip_pending()
1402 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >> in evergreen_get_temp()
1404 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >> in evergreen_get_temp()
1415 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> in evergreen_get_temp()
1436 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff; in sumo_get_temp()
1626 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); in evergreen_pm_prepare()
1651 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset); in evergreen_pm_finish()
1673 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE) in evergreen_hpd_sense()
1677 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE) in evergreen_hpd_sense()
1681 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE) in evergreen_hpd_sense()
1685 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE) in evergreen_hpd_sense()
1689 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE) in evergreen_hpd_sense()
1693 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE) in evergreen_hpd_sense()
1719 tmp = RREG32(DC_HPD1_INT_CONTROL); in evergreen_hpd_set_polarity()
1727 tmp = RREG32(DC_HPD2_INT_CONTROL); in evergreen_hpd_set_polarity()
1735 tmp = RREG32(DC_HPD3_INT_CONTROL); in evergreen_hpd_set_polarity()
1743 tmp = RREG32(DC_HPD4_INT_CONTROL); in evergreen_hpd_set_polarity()
1751 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_hpd_set_polarity()
1759 tmp = RREG32(DC_HPD6_INT_CONTROL); in evergreen_hpd_set_polarity()
1922 if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) & in evergreen_line_buffer_adjust()
1965 u32 tmp = RREG32(MC_SHARED_CHMAP); in evergreen_get_number_of_dram_channels()
2333 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); in evergreen_program_watermarks()
2342 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset); in evergreen_program_watermarks()
2412 tmp = RREG32(SRBM_STATUS) & 0x1F00; in evergreen_mc_wait_for_idle()
2433 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); in evergreen_pcie_gart_tlb_flush()
2620 dig_fe = RREG32(NI_DIG_FE_CNTL + ni_dig_offsets[i]); in evergreen_is_dp_sst_stream_enabled()
2634 dig_be = RREG32(NI_DIG_BE_CNTL + ni_dig_offsets[i]); in evergreen_is_dp_sst_stream_enabled()
2641 dig_en_be = RREG32(NI_DIG_BE_EN_CNTL + in evergreen_is_dp_sst_stream_enabled()
2643 uniphy_pll = RREG32(NI_DCIO_UNIPHY0_PLL_CONTROL1 + in evergreen_is_dp_sst_stream_enabled()
2676 stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL + in evergreen_blank_dp_output()
2687 stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL + in evergreen_blank_dp_output()
2692 stream_ctrl = RREG32(EVERGREEN_DP_VID_STREAM_CNTL + in evergreen_blank_dp_output()
2698 fifo_ctrl = RREG32(EVERGREEN_DP_STEER_FIFO + evergreen_dp_offsets[dig_fe]); in evergreen_blank_dp_output()
2711 save->vga_render_control = RREG32(VGA_RENDER_CONTROL); in evergreen_mc_stop()
2712 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); in evergreen_mc_stop()
2719 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; in evergreen_mc_stop()
2723 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()
2732 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()
2761 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()
2774 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); in evergreen_mc_stop()
2788 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in evergreen_mc_stop()
2793 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); in evergreen_mc_stop()
2827 tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]); in evergreen_mc_resume()
2833 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in evergreen_mc_resume()
2838 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]); in evergreen_mc_resume()
2844 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]); in evergreen_mc_resume()
2853 tmp = RREG32(MC_SHARED_BLACKOUT_CNTL); in evergreen_mc_resume()
2862 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); in evergreen_mc_resume()
2868 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); in evergreen_mc_resume()
2939 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF; in evergreen_mc_program()
3118 RREG32(GRBM_SOFT_RESET); in evergreen_cp_resume()
3121 RREG32(GRBM_SOFT_RESET); in evergreen_cp_resume()
3441 mc_shared_chmap = RREG32(MC_SHARED_CHMAP); in evergreen_gpu_init()
3445 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG); in evergreen_gpu_init()
3447 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); in evergreen_gpu_init()
3508 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16; in evergreen_gpu_init()
3529 simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; in evergreen_gpu_init()
3579 sx_debug_1 = RREG32(SX_DEBUG_1); in evergreen_gpu_init()
3584 smx_dc_ctl0 = RREG32(SMX_DC_CTL0); in evergreen_gpu_init()
3610 sq_config = RREG32(SQ_CONFIG); in evergreen_gpu_init()
3635 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT); in evergreen_gpu_init()
3737 tmp = RREG32(HDP_MISC_CNTL); in evergreen_gpu_init()
3741 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); in evergreen_gpu_init()
3760 tmp = RREG32(FUS_MC_ARB_RAMCFG); in evergreen_mc_init()
3762 tmp = RREG32(MC_ARB_RAMCFG); in evergreen_mc_init()
3770 tmp = RREG32(MC_SHARED_CHMAP); in evergreen_mc_init()
3795 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); in evergreen_mc_init()
3796 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); in evergreen_mc_init()
3799 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; in evergreen_mc_init()
3800 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; in evergreen_mc_init()
3812 RREG32(GRBM_STATUS)); in evergreen_print_gpu_status_regs()
3814 RREG32(GRBM_STATUS_SE0)); in evergreen_print_gpu_status_regs()
3816 RREG32(GRBM_STATUS_SE1)); in evergreen_print_gpu_status_regs()
3818 RREG32(SRBM_STATUS)); in evergreen_print_gpu_status_regs()
3820 RREG32(SRBM_STATUS2)); in evergreen_print_gpu_status_regs()
3822 RREG32(CP_STALLED_STAT1)); in evergreen_print_gpu_status_regs()
3824 RREG32(CP_STALLED_STAT2)); in evergreen_print_gpu_status_regs()
3826 RREG32(CP_BUSY_STAT)); in evergreen_print_gpu_status_regs()
3828 RREG32(CP_STAT)); in evergreen_print_gpu_status_regs()
3830 RREG32(DMA_STATUS_REG)); in evergreen_print_gpu_status_regs()
3833 RREG32(DMA_STATUS_REG + 0x800)); in evergreen_print_gpu_status_regs()
3844 if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN) { in evergreen_is_display_hung()
3845 crtc_status[i] = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in evergreen_is_display_hung()
3853 tmp = RREG32(EVERGREEN_CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in evergreen_is_display_hung()
3872 tmp = RREG32(GRBM_STATUS); in evergreen_gpu_check_soft_reset()
3888 tmp = RREG32(DMA_STATUS_REG); in evergreen_gpu_check_soft_reset()
3893 tmp = RREG32(SRBM_STATUS2); in evergreen_gpu_check_soft_reset()
3898 tmp = RREG32(SRBM_STATUS); in evergreen_gpu_check_soft_reset()
3922 tmp = RREG32(VM_L2_STATUS); in evergreen_gpu_check_soft_reset()
3953 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_soft_reset()
4013 tmp = RREG32(GRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4017 tmp = RREG32(GRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4023 tmp = RREG32(GRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4027 tmp = RREG32(SRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4031 tmp = RREG32(SRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4037 tmp = RREG32(SRBM_SOFT_RESET); in evergreen_gpu_soft_reset()
4062 tmp = RREG32(DMA_RB_CNTL); in evergreen_gpu_pci_config_reset()
4085 if (RREG32(CONFIG_MEMSIZE) != 0xffffffff) in evergreen_gpu_pci_config_reset()
4433 u32 tmp = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16; in evergreen_rlc_resume()
4490 return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]); in evergreen_get_vblank_counter()
4502 tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE; in evergreen_disable_interrupt_state()
4506 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_disable_interrupt_state()
4537 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4539 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4541 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4543 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4545 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4547 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4575 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in evergreen_irq_set()
4576 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in evergreen_irq_set()
4577 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in evergreen_irq_set()
4578 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in evergreen_irq_set()
4579 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in evergreen_irq_set()
4580 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in evergreen_irq_set()
4582 thermal_int = RREG32(TN_CG_THERMAL_INT_CTRL) & in evergreen_irq_set()
4585 thermal_int = RREG32(CG_THERMAL_INT) & in evergreen_irq_set()
4588 …afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRI… in evergreen_irq_set()
4589 …afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRI… in evergreen_irq_set()
4590 …afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRI… in evergreen_irq_set()
4591 …afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRI… in evergreen_irq_set()
4592 …afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRI… in evergreen_irq_set()
4593 …afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRI… in evergreen_irq_set()
4595 dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in evergreen_irq_set()
4625 dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE; in evergreen_irq_set()
4777 RREG32(SRBM_STATUS); in evergreen_irq_set()
4786 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS); in evergreen_irq_ack()
4787 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); in evergreen_irq_ack()
4788 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); in evergreen_irq_ack()
4789 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); in evergreen_irq_ack()
4790 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); in evergreen_irq_ack()
4791 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); in evergreen_irq_ack()
4792 …rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSE… in evergreen_irq_ack()
4793 …rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSE… in evergreen_irq_ack()
4795 …rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSE… in evergreen_irq_ack()
4796 …rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSE… in evergreen_irq_ack()
4799 …rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSE… in evergreen_irq_ack()
4800 …rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSE… in evergreen_irq_ack()
4803 rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET); in evergreen_irq_ack()
4804 rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET); in evergreen_irq_ack()
4805 rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET); in evergreen_irq_ack()
4806 rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET); in evergreen_irq_ack()
4807 rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET); in evergreen_irq_ack()
4808 rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET); in evergreen_irq_ack()
4854 tmp = RREG32(DC_HPD1_INT_CONTROL); in evergreen_irq_ack()
4859 tmp = RREG32(DC_HPD2_INT_CONTROL); in evergreen_irq_ack()
4864 tmp = RREG32(DC_HPD3_INT_CONTROL); in evergreen_irq_ack()
4869 tmp = RREG32(DC_HPD4_INT_CONTROL); in evergreen_irq_ack()
4874 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_irq_ack()
4879 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_irq_ack()
4885 tmp = RREG32(DC_HPD1_INT_CONTROL); in evergreen_irq_ack()
4890 tmp = RREG32(DC_HPD2_INT_CONTROL); in evergreen_irq_ack()
4895 tmp = RREG32(DC_HPD3_INT_CONTROL); in evergreen_irq_ack()
4900 tmp = RREG32(DC_HPD4_INT_CONTROL); in evergreen_irq_ack()
4905 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_irq_ack()
4910 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_irq_ack()
4916 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); in evergreen_irq_ack()
4921 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); in evergreen_irq_ack()
4926 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); in evergreen_irq_ack()
4931 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); in evergreen_irq_ack()
4936 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); in evergreen_irq_ack()
4941 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); in evergreen_irq_ack()
4969 wptr = RREG32(IH_RB_WPTR); in evergreen_get_ih_wptr()
4980 tmp = RREG32(IH_RB_CNTL); in evergreen_get_ih_wptr()
5373 DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); in evergreen_irq_process()
5382 addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR); in evergreen_irq_process()
5383 status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS); in evergreen_irq_process()