1079 	WREG32_P(cntl_reg, dividers.post_div, ~(DCLK_DIR_CNTL_EN|DCLK_DIVIDER_MASK));  in sumo_set_uvd_clock()
1122 	WREG32_P(CG_UPLL_FUNC_CNTL_2,  in evergreen_set_uvd_clocks()
1127 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);  in evergreen_set_uvd_clocks()
1131 		WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);  in evergreen_set_uvd_clocks()
1142 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_VCO_MODE_MASK, ~UPLL_VCO_MODE_MASK);  in evergreen_set_uvd_clocks()
1145 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);  in evergreen_set_uvd_clocks()
1146 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_SLEEP_MASK);  in evergreen_set_uvd_clocks()
1149 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);  in evergreen_set_uvd_clocks()
1158 	WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);  in evergreen_set_uvd_clocks()
1161 	WREG32_P(CG_UPLL_SPREAD_SPECTRUM, 0, ~SSEN_MASK);  in evergreen_set_uvd_clocks()
1164 	WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK);  in evergreen_set_uvd_clocks()
1167 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_REF_DIV_MASK);  in evergreen_set_uvd_clocks()
1170 		WREG32_P(CG_UPLL_FUNC_CNTL_4, 0, ~UPLL_SPARE_ISPARE9);  in evergreen_set_uvd_clocks()
1172 		WREG32_P(CG_UPLL_FUNC_CNTL_4, UPLL_SPARE_ISPARE9, ~UPLL_SPARE_ISPARE9);  in evergreen_set_uvd_clocks()
1175 	WREG32_P(CG_UPLL_FUNC_CNTL_2,  in evergreen_set_uvd_clocks()
1183 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);  in evergreen_set_uvd_clocks()
1188 	WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);  in evergreen_set_uvd_clocks()
1195 	WREG32_P(CG_UPLL_FUNC_CNTL_2,  in evergreen_set_uvd_clocks()
5385 			WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);  in evergreen_irq_process()