1223 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);  in dce4_program_fmt()  local
1271 	WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);  in dce4_program_fmt()
1346 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];  in evergreen_page_flip()  local
1347 	u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);  in evergreen_page_flip()
1352 	WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);  in evergreen_page_flip()
1355 	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1357 	WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1360 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1362 	WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in evergreen_page_flip()
1367 …if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDI…  in evergreen_page_flip()
1375 	WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);  in evergreen_page_flip()
1388 	struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];  in evergreen_page_flip_pending()  local
1391 	return !!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) &  in evergreen_page_flip_pending()
1619 	struct radeon_crtc *radeon_crtc;  in evergreen_pm_prepare()  local
1624 		radeon_crtc = to_radeon_crtc(crtc);  in evergreen_pm_prepare()
1625 		if (radeon_crtc->enabled) {  in evergreen_pm_prepare()
1626 			tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);  in evergreen_pm_prepare()
1628 			WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in evergreen_pm_prepare()
1644 	struct radeon_crtc *radeon_crtc;  in evergreen_pm_finish()  local
1649 		radeon_crtc = to_radeon_crtc(crtc);  in evergreen_pm_finish()
1650 		if (radeon_crtc->enabled) {  in evergreen_pm_finish()
1651 			tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);  in evergreen_pm_finish()
1653 			WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);  in evergreen_pm_finish()
1873 					struct radeon_crtc *radeon_crtc,  in evergreen_line_buffer_adjust()  argument
1878 	u32 pipe_offset = radeon_crtc->crtc_id * 0x20;  in evergreen_line_buffer_adjust()
1900 	if (radeon_crtc->base.enabled && mode) {  in evergreen_line_buffer_adjust()
1914 	if (radeon_crtc->crtc_id % 2)  in evergreen_line_buffer_adjust()
1916 	WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);  in evergreen_line_buffer_adjust()
1929 	if (radeon_crtc->base.enabled && mode) {  in evergreen_line_buffer_adjust()
2208 					 struct radeon_crtc *radeon_crtc,  in evergreen_program_watermarks()  argument
2211 	struct drm_display_mode *mode = &radeon_crtc->base.mode;  in evergreen_program_watermarks()
2220 	u32 pipe_offset = radeon_crtc->crtc_id * 16;  in evergreen_program_watermarks()
2224 	if (radeon_crtc->base.enabled && num_heads && mode) {  in evergreen_program_watermarks()
2249 		wm_high.vsc = radeon_crtc->vsc;  in evergreen_program_watermarks()
2251 		if (radeon_crtc->rmx_type != RMX_OFF)  in evergreen_program_watermarks()
2276 		wm_low.vsc = radeon_crtc->vsc;  in evergreen_program_watermarks()
2278 		if (radeon_crtc->rmx_type != RMX_OFF)  in evergreen_program_watermarks()
2312 		c.full = dfixed_mul(c, radeon_crtc->hsc);  in evergreen_program_watermarks()
2324 		c.full = dfixed_mul(c, radeon_crtc->hsc);  in evergreen_program_watermarks()
2353 	WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);  in evergreen_program_watermarks()
2354 	WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);  in evergreen_program_watermarks()
2357 	radeon_crtc->line_time = line_time;  in evergreen_program_watermarks()
2358 	radeon_crtc->wm_high = latency_watermark_a;  in evergreen_program_watermarks()
2359 	radeon_crtc->wm_low = latency_watermark_b;  in evergreen_program_watermarks()