3868 	u32 reset_mask = 0;  in evergreen_gpu_check_soft_reset()  local
3878 		reset_mask |= RADEON_RESET_GFX;  in evergreen_gpu_check_soft_reset()
3882 		reset_mask |= RADEON_RESET_CP;  in evergreen_gpu_check_soft_reset()
3885 		reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;  in evergreen_gpu_check_soft_reset()
3890 		reset_mask |= RADEON_RESET_DMA;  in evergreen_gpu_check_soft_reset()
3895 		reset_mask |= RADEON_RESET_DMA;  in evergreen_gpu_check_soft_reset()
3900 		reset_mask |= RADEON_RESET_RLC;  in evergreen_gpu_check_soft_reset()
3903 		reset_mask |= RADEON_RESET_IH;  in evergreen_gpu_check_soft_reset()
3906 		reset_mask |= RADEON_RESET_SEM;  in evergreen_gpu_check_soft_reset()
3909 		reset_mask |= RADEON_RESET_GRBM;  in evergreen_gpu_check_soft_reset()
3912 		reset_mask |= RADEON_RESET_VMC;  in evergreen_gpu_check_soft_reset()
3916 		reset_mask |= RADEON_RESET_MC;  in evergreen_gpu_check_soft_reset()
3919 		reset_mask |= RADEON_RESET_DISPLAY;  in evergreen_gpu_check_soft_reset()
3924 		reset_mask |= RADEON_RESET_VMC;  in evergreen_gpu_check_soft_reset()
3927 	if (reset_mask & RADEON_RESET_MC) {  in evergreen_gpu_check_soft_reset()
3928 		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);  in evergreen_gpu_check_soft_reset()
3929 		reset_mask &= ~RADEON_RESET_MC;  in evergreen_gpu_check_soft_reset()
3932 	return reset_mask;  in evergreen_gpu_check_soft_reset()
3935 static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)  in evergreen_gpu_soft_reset()  argument
3941 	if (reset_mask == 0)  in evergreen_gpu_soft_reset()
3944 	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);  in evergreen_gpu_soft_reset()
3951 	if (reset_mask & RADEON_RESET_DMA) {  in evergreen_gpu_soft_reset()
3965 	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {  in evergreen_gpu_soft_reset()
3979 	if (reset_mask & RADEON_RESET_CP) {  in evergreen_gpu_soft_reset()
3986 	if (reset_mask & RADEON_RESET_DMA)  in evergreen_gpu_soft_reset()
3989 	if (reset_mask & RADEON_RESET_DISPLAY)  in evergreen_gpu_soft_reset()
3992 	if (reset_mask & RADEON_RESET_RLC)  in evergreen_gpu_soft_reset()
3995 	if (reset_mask & RADEON_RESET_SEM)  in evergreen_gpu_soft_reset()
3998 	if (reset_mask & RADEON_RESET_IH)  in evergreen_gpu_soft_reset()
4001 	if (reset_mask & RADEON_RESET_GRBM)  in evergreen_gpu_soft_reset()
4004 	if (reset_mask & RADEON_RESET_VMC)  in evergreen_gpu_soft_reset()
4008 		if (reset_mask & RADEON_RESET_MC)  in evergreen_gpu_soft_reset()
4093 	u32 reset_mask;  in evergreen_asic_reset()  local
4095 	reset_mask = evergreen_gpu_check_soft_reset(rdev);  in evergreen_asic_reset()
4097 	if (reset_mask)  in evergreen_asic_reset()
4101 	evergreen_gpu_soft_reset(rdev, reset_mask);  in evergreen_asic_reset()
4103 	reset_mask = evergreen_gpu_check_soft_reset(rdev);  in evergreen_asic_reset()
4106 	if (reset_mask && radeon_hard_reset)  in evergreen_asic_reset()
4109 	reset_mask = evergreen_gpu_check_soft_reset(rdev);  in evergreen_asic_reset()
4111 	if (!reset_mask)  in evergreen_asic_reset()
4128 	u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);  in evergreen_gfx_is_lockup()  local
4130 	if (!(reset_mask & (RADEON_RESET_GFX |  in evergreen_gfx_is_lockup()