2758 	struct radeon_bo_list *src_reloc, *dst_reloc, *dst2_reloc;  in evergreen_dma_cs_parse()  local
2923 				r = r600_dma_cs_next_reloc(p, &dst2_reloc);  in evergreen_dma_cs_parse()
2944 				if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {  in evergreen_dma_cs_parse()
2946 							dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));  in evergreen_dma_cs_parse()
2950 				ib[idx+2] += (u32)(dst2_reloc->gpu_offset & 0xfffffffc);  in evergreen_dma_cs_parse()
2953 				ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff;  in evergreen_dma_cs_parse()
2963 				r = r600_dma_cs_next_reloc(p, &dst2_reloc);  in evergreen_dma_cs_parse()
2984 				if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {  in evergreen_dma_cs_parse()
2986 							dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));  in evergreen_dma_cs_parse()
2990 				ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
3025 				r = r600_dma_cs_next_reloc(p, &dst2_reloc);  in evergreen_dma_cs_parse()
3046 				if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {  in evergreen_dma_cs_parse()
3048 							dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));  in evergreen_dma_cs_parse()
3052 				ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()
3112 				r = r600_dma_cs_next_reloc(p, &dst2_reloc);  in evergreen_dma_cs_parse()
3133 				if ((dst2_offset + (count * 4)) > radeon_bo_size(dst2_reloc->robj)) {  in evergreen_dma_cs_parse()
3135 							dst2_offset + (count * 4), radeon_bo_size(dst2_reloc->robj));  in evergreen_dma_cs_parse()
3139 				ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8);  in evergreen_dma_cs_parse()