Lines Matching refs:dst_reloc
2758 struct radeon_bo_list *src_reloc, *dst_reloc, *dst2_reloc; in evergreen_dma_cs_parse() local
2779 r = r600_dma_cs_next_reloc(p, &dst_reloc); in evergreen_dma_cs_parse()
2790 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2798 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2799 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2806 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2808 dst_offset, radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2818 r = r600_dma_cs_next_reloc(p, &dst_reloc); in evergreen_dma_cs_parse()
2836 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2838 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2841 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2843 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2858 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2859 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2869 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2876 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2878 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2895 if ((dst_offset + count) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2897 dst_offset + count, radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2900 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2902 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2915 ib[idx+4] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2916 ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2939 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2941 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2949 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2952 ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2979 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
2981 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
2989 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3007 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3008 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3014 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3041 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3043 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3051 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3069 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3070 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3080 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3087 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3089 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3102 ib[idx+4] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3128 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3130 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3138 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3150 r = r600_dma_cs_next_reloc(p, &dst_reloc); in evergreen_dma_cs_parse()
3157 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) { in evergreen_dma_cs_parse()
3159 dst_offset, radeon_bo_size(dst_reloc->robj)); in evergreen_dma_cs_parse()
3162 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3163 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; in evergreen_dma_cs_parse()