Lines Matching refs:ib
447 volatile u32 *ib = p->ib.ptr; in evergreen_cs_track_validate_cb() local
469 ib[track->cb_color_slice_idx[id]] = slice; in evergreen_cs_track_validate_cb()
1100 u32 m, i, tmp, *ib; in evergreen_cs_check_reg() local
1121 ib = p->ib.ptr; in evergreen_cs_check_reg()
1169 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1198 ib[idx] &= ~Z_ARRAY_MODE(0xf); in evergreen_cs_check_reg()
1200 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_check_reg()
1208 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_check_reg()
1209 ib[idx] |= DB_TILE_SPLIT(tile_split) | in evergreen_cs_check_reg()
1241 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1253 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1265 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1277 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1301 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1321 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1385 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_check_reg()
1403 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_check_reg()
1471 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_check_reg()
1472 ib[idx] |= CB_TILE_SPLIT(tile_split) | in evergreen_cs_check_reg()
1479 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_check_reg()
1499 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_check_reg()
1500 ib[idx] |= CB_TILE_SPLIT(tile_split) | in evergreen_cs_check_reg()
1507 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_check_reg()
1524 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1541 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1582 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1598 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1610 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1618 ib[idx] |= 3; in evergreen_cs_check_reg()
1727 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1741 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1755 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1798 volatile u32 *ib; in evergreen_packet3_check() local
1806 ib = p->ib.ptr; in evergreen_packet3_check()
1844 ib[idx + 0] = offset; in evergreen_packet3_check()
1845 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
1890 ib[idx+0] = offset; in evergreen_packet3_check()
1891 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1925 ib[idx+0] = offset; in evergreen_packet3_check()
1926 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1953 ib[idx+1] = offset; in evergreen_packet3_check()
1954 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2046 ib[idx+1] = reloc->gpu_offset; in evergreen_packet3_check()
2047 ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff; in evergreen_packet3_check()
2100 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); in evergreen_packet3_check()
2126 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc); in evergreen_packet3_check()
2127 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2187 ib[idx] = offset; in evergreen_packet3_check()
2188 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2225 ib[idx+2] = offset; in evergreen_packet3_check()
2226 ib[idx+3] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2247 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2267 ib[idx+1] = offset & 0xfffffff8; in evergreen_packet3_check()
2268 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2289 ib[idx+1] = offset & 0xfffffffc; in evergreen_packet3_check()
2290 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2311 ib[idx+1] = offset & 0xfffffffc; in evergreen_packet3_check()
2312 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2374 ib[idx+1+(i*8)+1] |= in evergreen_packet3_check()
2382 ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split); in evergreen_packet3_check()
2383 ib[idx+1+(i*8)+7] |= in evergreen_packet3_check()
2394 tex_dim = ib[idx+1+(i*8)+0] & 0x7; in evergreen_packet3_check()
2395 mip_address = ib[idx+1+(i*8)+3]; in evergreen_packet3_check()
2417 ib[idx+1+(i*8)+2] += toffset; in evergreen_packet3_check()
2418 ib[idx+1+(i*8)+3] += moffset; in evergreen_packet3_check()
2434 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset; in evergreen_packet3_check()
2438 ib[idx+1+(i*8)+0] = offset64; in evergreen_packet3_check()
2439 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | in evergreen_packet3_check()
2519 ib[idx+1] = offset; in evergreen_packet3_check()
2520 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2538 ib[idx+3] = offset; in evergreen_packet3_check()
2539 ib[idx+4] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2567 ib[idx+0] = offset; in evergreen_packet3_check()
2568 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2592 ib[idx+1] = offset; in evergreen_packet3_check()
2593 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2616 ib[idx+3] = offset; in evergreen_packet3_check()
2617 ib[idx+4] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2736 for (r = 0; r < p->ib.length_dw; r++) { in evergreen_cs_parse()
2737 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]); in evergreen_cs_parse()
2760 volatile u32 *ib = p->ib.ptr; in evergreen_dma_cs_parse() local
2790 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2798 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2799 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2841 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2842 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2843 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2844 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2854 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2858 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2859 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2864 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2865 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2869 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2900 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2901 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2902 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2903 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2913 ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2914 ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2915 ib[idx+4] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2916 ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2949 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2950 ib[idx+2] += (u32)(dst2_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2951 ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2952 ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2953 ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2954 ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2989 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2990 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2991 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2992 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3005 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3007 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3008 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3011 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3012 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3014 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3051 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3052 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3053 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3054 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3065 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3069 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3070 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3075 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3076 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3080 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3101 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3102 ib[idx+4] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3138 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3139 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3140 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3141 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3162 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3163 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; in evergreen_dma_cs_parse()
3175 for (r = 0; r < p->ib->length_dw; r++) { in evergreen_dma_cs_parse()
3176 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]); in evergreen_dma_cs_parse()
3307 u32 *ib, struct radeon_cs_packet *pkt) in evergreen_vm_packet3_check() argument
3310 u32 idx_value = ib[idx]; in evergreen_vm_packet3_check()
3366 reg = ib[idx + 5] * 4; in evergreen_vm_packet3_check()
3373 reg = ib[idx + 3] * 4; in evergreen_vm_packet3_check()
3394 command = ib[idx + 4]; in evergreen_vm_packet3_check()
3395 info = ib[idx + 1]; in evergreen_vm_packet3_check()
3432 start_reg = ib[idx + 2]; in evergreen_vm_packet3_check()
3457 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) in evergreen_ib_parse() argument
3465 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]); in evergreen_ib_parse()
3466 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]); in evergreen_ib_parse()
3477 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]); in evergreen_ib_parse()
3478 ret = evergreen_vm_packet3_check(rdev, ib->ptr, &pkt); in evergreen_ib_parse()
3488 } while (idx < ib->length_dw); in evergreen_ib_parse()
3502 int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib) in evergreen_dma_ib_parse() argument
3508 header = ib->ptr[idx]; in evergreen_dma_ib_parse()
3525 DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, ib->ptr[idx]); in evergreen_dma_ib_parse()
3576 DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, ib->ptr[idx]); in evergreen_dma_ib_parse()
3590 } while (idx < ib->length_dw); in evergreen_dma_ib_parse()