Lines Matching refs:idx
752 unsigned idx) in evergreen_cs_track_validate_texture() argument
760 texdw[0] = radeon_get_ib_value(p, idx + 0); in evergreen_cs_track_validate_texture()
761 texdw[1] = radeon_get_ib_value(p, idx + 1); in evergreen_cs_track_validate_texture()
762 texdw[2] = radeon_get_ib_value(p, idx + 2); in evergreen_cs_track_validate_texture()
763 texdw[3] = radeon_get_ib_value(p, idx + 3); in evergreen_cs_track_validate_texture()
764 texdw[4] = radeon_get_ib_value(p, idx + 4); in evergreen_cs_track_validate_texture()
765 texdw[5] = radeon_get_ib_value(p, idx + 5); in evergreen_cs_track_validate_texture()
766 texdw[6] = radeon_get_ib_value(p, idx + 6); in evergreen_cs_track_validate_texture()
767 texdw[7] = radeon_get_ib_value(p, idx + 7); in evergreen_cs_track_validate_texture()
1046 unsigned idx, unsigned reg) in evergreen_packet0_check() argument
1055 idx, reg); in evergreen_packet0_check()
1061 reg, idx); in evergreen_packet0_check()
1071 unsigned idx; in evergreen_cs_parse_packet0() local
1074 idx = pkt->idx + 1; in evergreen_cs_parse_packet0()
1076 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) { in evergreen_cs_parse_packet0()
1077 r = evergreen_packet0_check(p, pkt, idx, reg); in evergreen_cs_parse_packet0()
1095 static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) in evergreen_cs_check_reg() argument
1110 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in evergreen_cs_check_reg()
1169 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1172 track->db_depth_control = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1190 track->db_z_info = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1198 ib[idx] &= ~Z_ARRAY_MODE(0xf); in evergreen_cs_check_reg()
1200 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_check_reg()
1208 ib[idx] |= DB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_check_reg()
1209 ib[idx] |= DB_TILE_SPLIT(tile_split) | in evergreen_cs_check_reg()
1218 track->db_s_info = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1222 track->db_depth_view = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1226 track->db_depth_size = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1230 track->db_depth_slice = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1240 track->db_z_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1241 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1252 track->db_z_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1253 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1264 track->db_s_read_offset = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1265 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1276 track->db_s_write_offset = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1277 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1282 track->vgt_strmout_config = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1286 track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1300 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8; in evergreen_cs_check_reg()
1301 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1311 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4; in evergreen_cs_check_reg()
1321 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1323 track->cb_target_mask = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1327 track->cb_shader_mask = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1336 tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK; in evergreen_cs_check_reg()
1345 tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK; in evergreen_cs_check_reg()
1357 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1365 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1377 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1385 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_check_reg()
1395 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1403 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->tiling_flags)); in evergreen_cs_check_reg()
1417 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1425 track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1437 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1438 track->cb_color_slice_idx[tmp] = idx; in evergreen_cs_check_reg()
1446 track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1447 track->cb_color_slice_idx[tmp] = idx; in evergreen_cs_check_reg()
1471 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_check_reg()
1472 ib[idx] |= CB_TILE_SPLIT(tile_split) | in evergreen_cs_check_reg()
1479 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_check_reg()
1499 ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); in evergreen_cs_check_reg()
1500 ib[idx] |= CB_TILE_SPLIT(tile_split) | in evergreen_cs_check_reg()
1507 track->cb_color_attrib[tmp] = ib[idx]; in evergreen_cs_check_reg()
1524 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1541 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1553 track->cb_color_fmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1564 track->cb_color_cmask_slice[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1581 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1582 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1597 track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1598 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1609 track->htile_offset = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1610 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1616 track->htile_surface = radeon_get_ib_value(p, idx); in evergreen_cs_check_reg()
1618 ib[idx] |= 3; in evergreen_cs_check_reg()
1727 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1741 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1755 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_cs_check_reg()
1758 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0; in evergreen_cs_check_reg()
1761 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in evergreen_cs_check_reg()
1767 static bool evergreen_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) in evergreen_is_safe_reg() argument
1778 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in evergreen_is_safe_reg()
1789 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); in evergreen_is_safe_reg()
1799 unsigned idx; in evergreen_packet3_check() local
1807 idx = pkt->idx + 1; in evergreen_packet3_check()
1808 idx_value = radeon_get_ib_value(p, idx); in evergreen_packet3_check()
1822 tmp = radeon_get_ib_value(p, idx + 1); in evergreen_packet3_check()
1844 ib[idx + 0] = offset; in evergreen_packet3_check()
1845 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
1888 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
1890 ib[idx+0] = offset; in evergreen_packet3_check()
1891 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1923 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
1925 ib[idx+0] = offset; in evergreen_packet3_check()
1926 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1950 radeon_get_ib_value(p, idx+1) + in evergreen_packet3_check()
1951 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
1953 ib[idx+1] = offset; in evergreen_packet3_check()
1954 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1970 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
1981 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
2046 ib[idx+1] = reloc->gpu_offset; in evergreen_packet3_check()
2047 ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff; in evergreen_packet3_check()
2086 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx); in evergreen_packet3_check()
2100 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); in evergreen_packet3_check()
2123 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2124 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2126 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffffc); in evergreen_packet3_check()
2127 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2141 command = radeon_get_ib_value(p, idx+4); in evergreen_packet3_check()
2143 info = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2176 tmp = radeon_get_ib_value(p, idx) + in evergreen_packet3_check()
2177 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32); in evergreen_packet3_check()
2187 ib[idx] = offset; in evergreen_packet3_check()
2188 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2214 tmp = radeon_get_ib_value(p, idx+2) + in evergreen_packet3_check()
2215 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32); in evergreen_packet3_check()
2225 ib[idx+2] = offset; in evergreen_packet3_check()
2226 ib[idx+3] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2240 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff || in evergreen_packet3_check()
2241 radeon_get_ib_value(p, idx + 2) != 0) { in evergreen_packet3_check()
2247 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in evergreen_packet3_check()
2264 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) + in evergreen_packet3_check()
2265 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2267 ib[idx+1] = offset & 0xfffffff8; in evergreen_packet3_check()
2268 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2286 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2287 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2289 ib[idx+1] = offset & 0xfffffffc; in evergreen_packet3_check()
2290 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2308 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) + in evergreen_packet3_check()
2309 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32); in evergreen_packet3_check()
2311 ib[idx+1] = offset & 0xfffffffc; in evergreen_packet3_check()
2312 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2326 r = evergreen_cs_check_reg(p, reg, idx+1+i); in evergreen_packet3_check()
2342 r = evergreen_cs_check_reg(p, reg, idx+1+i); in evergreen_packet3_check()
2365 switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) { in evergreen_packet3_check()
2374 ib[idx+1+(i*8)+1] |= in evergreen_packet3_check()
2382 ib[idx+1+(i*8)+6] |= TEX_TILE_SPLIT(tile_split); in evergreen_packet3_check()
2383 ib[idx+1+(i*8)+7] |= in evergreen_packet3_check()
2394 tex_dim = ib[idx+1+(i*8)+0] & 0x7; in evergreen_packet3_check()
2395 mip_address = ib[idx+1+(i*8)+3]; in evergreen_packet3_check()
2414 r = evergreen_cs_track_validate_texture(p, texture, mipmap, idx+1+(i*8)); in evergreen_packet3_check()
2417 ib[idx+1+(i*8)+2] += toffset; in evergreen_packet3_check()
2418 ib[idx+1+(i*8)+3] += moffset; in evergreen_packet3_check()
2429 offset = radeon_get_ib_value(p, idx+1+(i*8)+0); in evergreen_packet3_check()
2430 size = radeon_get_ib_value(p, idx+1+(i*8)+1); in evergreen_packet3_check()
2434 ib[idx+1+(i*8)+1] = radeon_bo_size(reloc->robj) - offset; in evergreen_packet3_check()
2438 ib[idx+1+(i*8)+0] = offset64; in evergreen_packet3_check()
2439 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | in evergreen_packet3_check()
2511 offset = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2512 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_packet3_check()
2519 ib[idx+1] = offset; in evergreen_packet3_check()
2520 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2530 offset = radeon_get_ib_value(p, idx+3); in evergreen_packet3_check()
2531 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_packet3_check()
2538 ib[idx+3] = offset; in evergreen_packet3_check()
2539 ib[idx+4] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2555 offset = radeon_get_ib_value(p, idx+0); in evergreen_packet3_check()
2556 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL; in evergreen_packet3_check()
2567 ib[idx+0] = offset; in evergreen_packet3_check()
2568 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2584 offset = radeon_get_ib_value(p, idx+1); in evergreen_packet3_check()
2585 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_packet3_check()
2592 ib[idx+1] = offset; in evergreen_packet3_check()
2593 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2596 reg = radeon_get_ib_value(p, idx+1) << 2; in evergreen_packet3_check()
2597 if (!evergreen_is_safe_reg(p, reg, idx+1)) in evergreen_packet3_check()
2608 offset = radeon_get_ib_value(p, idx+3); in evergreen_packet3_check()
2609 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_packet3_check()
2616 ib[idx+3] = offset; in evergreen_packet3_check()
2617 ib[idx+4] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2620 reg = radeon_get_ib_value(p, idx+3) << 2; in evergreen_packet3_check()
2621 if (!evergreen_is_safe_reg(p, reg, idx+3)) in evergreen_packet3_check()
2707 r = radeon_cs_packet_parse(p, &pkt, p->idx); in evergreen_cs_parse()
2713 p->idx += pkt.count + 2; in evergreen_cs_parse()
2734 } while (p->idx < p->chunk_ib->length_dw); in evergreen_cs_parse()
2761 u32 idx; in evergreen_dma_cs_parse() local
2766 if (p->idx >= ib_chunk->length_dw) { in evergreen_dma_cs_parse()
2768 p->idx, ib_chunk->length_dw); in evergreen_dma_cs_parse()
2771 idx = p->idx; in evergreen_dma_cs_parse()
2772 header = radeon_get_ib_value(p, idx); in evergreen_dma_cs_parse()
2787 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2790 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2791 p->idx += count + 7; in evergreen_dma_cs_parse()
2795 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2796 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32; in evergreen_dma_cs_parse()
2798 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2799 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2800 p->idx += count + 3; in evergreen_dma_cs_parse()
2803 DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, header); in evergreen_dma_cs_parse()
2827 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2828 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2829 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2830 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in evergreen_dma_cs_parse()
2841 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2842 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2843 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2844 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2845 p->idx += 5; in evergreen_dma_cs_parse()
2850 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
2852 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2854 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2856 dst_offset = radeon_get_ib_value(p, idx + 7); in evergreen_dma_cs_parse()
2857 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
2858 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2859 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2862 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
2863 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
2864 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2865 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2867 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2869 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2881 p->idx += 9; in evergreen_dma_cs_parse()
2886 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2887 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2888 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2889 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in evergreen_dma_cs_parse()
2900 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2901 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2902 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2903 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2904 p->idx += 5; in evergreen_dma_cs_parse()
2913 ib[idx+1] += (u32)(src_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2914 ib[idx+2] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2915 ib[idx+4] += (u32)(dst_reloc->gpu_offset & 0xffffffff); in evergreen_dma_cs_parse()
2916 ib[idx+5] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2918 p->idx += 9; in evergreen_dma_cs_parse()
2928 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2929 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2930 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2931 dst2_offset |= ((u64)(radeon_get_ib_value(p, idx+5) & 0xff)) << 32; in evergreen_dma_cs_parse()
2932 src_offset = radeon_get_ib_value(p, idx+3); in evergreen_dma_cs_parse()
2933 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; in evergreen_dma_cs_parse()
2949 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2950 ib[idx+2] += (u32)(dst2_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2951 ib[idx+3] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2952 ib[idx+4] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2953 ib[idx+5] += upper_32_bits(dst2_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2954 ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2955 p->idx += 7; in evergreen_dma_cs_parse()
2959 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
2968 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2970 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2972 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
2973 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
2989 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2990 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
2991 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
2992 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
2993 p->idx += 10; in evergreen_dma_cs_parse()
3003 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3005 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3007 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3008 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3011 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3012 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3014 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3016 p->idx += 12; in evergreen_dma_cs_parse()
3021 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3030 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3032 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3034 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3035 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3051 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3052 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3053 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3054 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3055 p->idx += 10; in evergreen_dma_cs_parse()
3061 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3063 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3065 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3067 dst_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
3068 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3069 ib[idx+7] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3070 ib[idx+8] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3073 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
3074 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
3075 ib[idx+7] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3076 ib[idx+8] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3078 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3080 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3092 p->idx += 9; in evergreen_dma_cs_parse()
3101 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3102 ib[idx+4] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3103 p->idx += 13; in evergreen_dma_cs_parse()
3108 if (radeon_get_ib_value(p, idx + 2) & (1 << 31)) { in evergreen_dma_cs_parse()
3117 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3119 dst2_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
3121 src_offset = radeon_get_ib_value(p, idx+8); in evergreen_dma_cs_parse()
3122 src_offset |= ((u64)(radeon_get_ib_value(p, idx+9) & 0xff)) << 32; in evergreen_dma_cs_parse()
3138 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3139 ib[idx+2] += (u32)(dst2_reloc->gpu_offset >> 8); in evergreen_dma_cs_parse()
3140 ib[idx+8] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3141 ib[idx+9] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in evergreen_dma_cs_parse()
3142 p->idx += 10; in evergreen_dma_cs_parse()
3145 DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, header); in evergreen_dma_cs_parse()
3155 dst_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
3156 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16; in evergreen_dma_cs_parse()
3162 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in evergreen_dma_cs_parse()
3163 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; in evergreen_dma_cs_parse()
3164 p->idx += 4; in evergreen_dma_cs_parse()
3167 p->idx += 1; in evergreen_dma_cs_parse()
3170 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx); in evergreen_dma_cs_parse()
3173 } while (p->idx < p->chunk_ib->length_dw); in evergreen_dma_cs_parse()
3309 u32 idx = pkt->idx + 1; in evergreen_vm_packet3_check() local
3310 u32 idx_value = ib[idx]; in evergreen_vm_packet3_check()
3366 reg = ib[idx + 5] * 4; in evergreen_vm_packet3_check()
3373 reg = ib[idx + 3] * 4; in evergreen_vm_packet3_check()
3394 command = ib[idx + 4]; in evergreen_vm_packet3_check()
3395 info = ib[idx + 1]; in evergreen_vm_packet3_check()
3432 start_reg = ib[idx + 2]; in evergreen_vm_packet3_check()
3460 u32 idx = 0; in evergreen_ib_parse() local
3464 pkt.idx = idx; in evergreen_ib_parse()
3465 pkt.type = RADEON_CP_PACKET_GET_TYPE(ib->ptr[idx]); in evergreen_ib_parse()
3466 pkt.count = RADEON_CP_PACKET_GET_COUNT(ib->ptr[idx]); in evergreen_ib_parse()
3474 idx += 1; in evergreen_ib_parse()
3477 pkt.opcode = RADEON_CP_PACKET3_GET_OPCODE(ib->ptr[idx]); in evergreen_ib_parse()
3479 idx += pkt.count + 2; in evergreen_ib_parse()
3488 } while (idx < ib->length_dw); in evergreen_ib_parse()
3504 u32 idx = 0; in evergreen_dma_ib_parse() local
3508 header = ib->ptr[idx]; in evergreen_dma_ib_parse()
3518 idx += count + 7; in evergreen_dma_ib_parse()
3522 idx += count + 3; in evergreen_dma_ib_parse()
3525 DRM_ERROR("bad DMA_PACKET_WRITE [%6d] 0x%08x sub cmd is not 0 or 8\n", idx, ib->ptr[idx]); in evergreen_dma_ib_parse()
3533 idx += 5; in evergreen_dma_ib_parse()
3537 idx += 9; in evergreen_dma_ib_parse()
3541 idx += 5; in evergreen_dma_ib_parse()
3545 idx += 9; in evergreen_dma_ib_parse()
3549 idx += 7; in evergreen_dma_ib_parse()
3553 idx += 10; in evergreen_dma_ib_parse()
3557 idx += 12; in evergreen_dma_ib_parse()
3561 idx += 10; in evergreen_dma_ib_parse()
3565 idx += 9; in evergreen_dma_ib_parse()
3569 idx += 13; in evergreen_dma_ib_parse()
3573 idx += 10; in evergreen_dma_ib_parse()
3576 DRM_ERROR("bad DMA_PACKET_COPY [%6d] 0x%08x invalid sub cmd\n", idx, ib->ptr[idx]); in evergreen_dma_ib_parse()
3581 idx += 4; in evergreen_dma_ib_parse()
3584 idx += 1; in evergreen_dma_ib_parse()
3587 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx); in evergreen_dma_ib_parse()
3590 } while (idx < ib->length_dw); in evergreen_dma_ib_parse()