643 	mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;  in ni_mc_load_microcode()
644 	running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;  in ni_mc_load_microcode()
648 			blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);  in ni_mc_load_microcode()
673 			if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)  in ni_mc_load_microcode()
853 		*val = RREG32(reg);  in cayman_get_allowed_info_register()
999 	mc_shared_chmap = RREG32(MC_SHARED_CHMAP);  in cayman_gpu_init()
1000 	mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);  in cayman_gpu_init()
1077 		rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;  in cayman_gpu_init()
1097 		simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;  in cayman_gpu_init()
1145 	cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);  in cayman_gpu_init()
1153 	sx_debug_1 = RREG32(SX_DEBUG_1);  in cayman_gpu_init()
1157 	smx_dc_ctl0 = RREG32(SMX_DC_CTL0);  in cayman_gpu_init()
1219 	tmp = RREG32(HDP_MISC_CNTL);  in cayman_gpu_init()
1223 	hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);  in cayman_gpu_init()
1342 		rdev->vm_manager.saved_table_addr[i] = RREG32(  in cayman_pcie_gart_disable()
1374 	u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;  in cayman_cp_int_cntl_setup()
1464 			rptr = RREG32(CP_RB0_RPTR);  in cayman_gfx_get_rptr()
1466 			rptr = RREG32(CP_RB1_RPTR);  in cayman_gfx_get_rptr()
1468 			rptr = RREG32(CP_RB2_RPTR);  in cayman_gfx_get_rptr()
1480 		wptr = RREG32(CP_RB0_WPTR);  in cayman_gfx_get_wptr()
1482 		wptr = RREG32(CP_RB1_WPTR);  in cayman_gfx_get_wptr()
1484 		wptr = RREG32(CP_RB2_WPTR);  in cayman_gfx_get_wptr()
1494 		(void)RREG32(CP_RB0_WPTR);  in cayman_gfx_set_wptr()
1497 		(void)RREG32(CP_RB1_WPTR);  in cayman_gfx_set_wptr()
1500 		(void)RREG32(CP_RB2_WPTR);  in cayman_gfx_set_wptr()
1652 	RREG32(GRBM_SOFT_RESET);  in cayman_cp_resume()
1655 	RREG32(GRBM_SOFT_RESET);  in cayman_cp_resume()
1733 	tmp = RREG32(GRBM_STATUS);  in cayman_gpu_check_soft_reset()
1750 	tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);  in cayman_gpu_check_soft_reset()
1755 	tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);  in cayman_gpu_check_soft_reset()
1760 	tmp = RREG32(SRBM_STATUS2);  in cayman_gpu_check_soft_reset()
1768 	tmp = RREG32(SRBM_STATUS);  in cayman_gpu_check_soft_reset()
1792 	tmp = RREG32(VM_L2_STATUS);  in cayman_gpu_check_soft_reset()
1818 		 RREG32(0x14F8));  in cayman_gpu_soft_reset()
1820 		 RREG32(0x14D8));  in cayman_gpu_soft_reset()
1822 		 RREG32(0x14FC));  in cayman_gpu_soft_reset()
1824 		 RREG32(0x14DC));  in cayman_gpu_soft_reset()
1831 		tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);  in cayman_gpu_soft_reset()
1838 		tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);  in cayman_gpu_soft_reset()
1901 		tmp = RREG32(GRBM_SOFT_RESET);  in cayman_gpu_soft_reset()
1905 		tmp = RREG32(GRBM_SOFT_RESET);  in cayman_gpu_soft_reset()
1911 		tmp = RREG32(GRBM_SOFT_RESET);  in cayman_gpu_soft_reset()
1915 		tmp = RREG32(SRBM_SOFT_RESET);  in cayman_gpu_soft_reset()
1919 		tmp = RREG32(SRBM_SOFT_RESET);  in cayman_gpu_soft_reset()
1925 		tmp = RREG32(SRBM_SOFT_RESET);  in cayman_gpu_soft_reset()
2348 		u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);  in cayman_vm_init()