649 			WREG32(MC_SHARED_BLACKOUT_CNTL, 1);  in ni_mc_load_microcode()
653 		WREG32(MC_SEQ_SUP_CNTL, 0x00000008);  in ni_mc_load_microcode()
654 		WREG32(MC_SEQ_SUP_CNTL, 0x00000010);  in ni_mc_load_microcode()
658 			WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);  in ni_mc_load_microcode()
659 			WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);  in ni_mc_load_microcode()
664 			WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));  in ni_mc_load_microcode()
667 		WREG32(MC_SEQ_SUP_CNTL, 0x00000008);  in ni_mc_load_microcode()
668 		WREG32(MC_SEQ_SUP_CNTL, 0x00000004);  in ni_mc_load_microcode()
669 		WREG32(MC_SEQ_SUP_CNTL, 0x00000001);  in ni_mc_load_microcode()
679 			WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);  in ni_mc_load_microcode()
986 		WREG32((0x2c14 + j), 0x00000000);  in cayman_gpu_init()
987 		WREG32((0x2c18 + j), 0x00000000);  in cayman_gpu_init()
988 		WREG32((0x2c1c + j), 0x00000000);  in cayman_gpu_init()
989 		WREG32((0x2c20 + j), 0x00000000);  in cayman_gpu_init()
990 		WREG32((0x2c24 + j), 0x00000000);  in cayman_gpu_init()
993 	WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));  in cayman_gpu_init()
994 	WREG32(SRBM_INT_CNTL, 0x1);  in cayman_gpu_init()
995 	WREG32(SRBM_INT_ACK, 0x1);  in cayman_gpu_init()
1075 		WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));  in cayman_gpu_init()
1076 		WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));  in cayman_gpu_init()
1095 		WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));  in cayman_gpu_init()
1096 		WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));  in cayman_gpu_init()
1104 	WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);  in cayman_gpu_init()
1105 	WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);  in cayman_gpu_init()
1107 	WREG32(GB_ADDR_CONFIG, gb_addr_config);  in cayman_gpu_init()
1108 	WREG32(DMIF_ADDR_CONFIG, gb_addr_config);  in cayman_gpu_init()
1110 		WREG32(DMIF_ADDR_CALC, gb_addr_config);  in cayman_gpu_init()
1111 	WREG32(HDP_ADDR_CONFIG, gb_addr_config);  in cayman_gpu_init()
1112 	WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);  in cayman_gpu_init()
1113 	WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);  in cayman_gpu_init()
1114 	WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);  in cayman_gpu_init()
1115 	WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);  in cayman_gpu_init()
1116 	WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);  in cayman_gpu_init()
1134 	WREG32(GB_BACKEND_MAP, tmp);  in cayman_gpu_init()
1139 	WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);  in cayman_gpu_init()
1140 	WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);  in cayman_gpu_init()
1141 	WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);  in cayman_gpu_init()
1142 	WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);  in cayman_gpu_init()
1147 		WREG32(CGTS_SM_CTRL_REG, OVERRIDE);  in cayman_gpu_init()
1148 	WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);  in cayman_gpu_init()
1151 	WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));  in cayman_gpu_init()
1155 	WREG32(SX_DEBUG_1, sx_debug_1);  in cayman_gpu_init()
1160 	WREG32(SMX_DC_CTL0, smx_dc_ctl0);  in cayman_gpu_init()
1162 	WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);  in cayman_gpu_init()
1165 	WREG32(VGT_OFFCHIP_LDS_BASE, 0);  in cayman_gpu_init()
1166 	WREG32(SQ_LSTMP_RING_BASE, 0);  in cayman_gpu_init()
1167 	WREG32(SQ_HSTMP_RING_BASE, 0);  in cayman_gpu_init()
1168 	WREG32(SQ_ESTMP_RING_BASE, 0);  in cayman_gpu_init()
1169 	WREG32(SQ_GSTMP_RING_BASE, 0);  in cayman_gpu_init()
1170 	WREG32(SQ_VSTMP_RING_BASE, 0);  in cayman_gpu_init()
1171 	WREG32(SQ_PSTMP_RING_BASE, 0);  in cayman_gpu_init()
1173 	WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);  in cayman_gpu_init()
1175 …WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1…  in cayman_gpu_init()
1179 	WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |  in cayman_gpu_init()
1184 	WREG32(VGT_NUM_INSTANCES, 1);  in cayman_gpu_init()
1186 	WREG32(CP_PERFMON_CNTL, 0);  in cayman_gpu_init()
1188 	WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |  in cayman_gpu_init()
1193 	WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));  in cayman_gpu_init()
1194 	WREG32(SQ_CONFIG, (VC_ENABLE |  in cayman_gpu_init()
1199 	WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);  in cayman_gpu_init()
1201 	WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |  in cayman_gpu_init()
1204 	WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |  in cayman_gpu_init()
1207 	WREG32(VGT_GS_VERTEX_REUSE, 16);  in cayman_gpu_init()
1208 	WREG32(PA_SC_LINE_STIPPLE_STATE, 0);  in cayman_gpu_init()
1210 	WREG32(CB_PERF_CTR0_SEL_0, 0);  in cayman_gpu_init()
1211 	WREG32(CB_PERF_CTR0_SEL_1, 0);  in cayman_gpu_init()
1212 	WREG32(CB_PERF_CTR1_SEL_0, 0);  in cayman_gpu_init()
1213 	WREG32(CB_PERF_CTR1_SEL_1, 0);  in cayman_gpu_init()
1214 	WREG32(CB_PERF_CTR2_SEL_0, 0);  in cayman_gpu_init()
1215 	WREG32(CB_PERF_CTR2_SEL_1, 0);  in cayman_gpu_init()
1216 	WREG32(CB_PERF_CTR3_SEL_0, 0);  in cayman_gpu_init()
1217 	WREG32(CB_PERF_CTR3_SEL_1, 0);  in cayman_gpu_init()
1221 	WREG32(HDP_MISC_CNTL, tmp);  in cayman_gpu_init()
1224 	WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);  in cayman_gpu_init()
1226 	WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));  in cayman_gpu_init()
1247 	WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);  in cayman_pcie_gart_tlb_flush()
1250 	WREG32(VM_INVALIDATE_REQUEST, 1);  in cayman_pcie_gart_tlb_flush()
1265 	WREG32(MC_VM_MX_L1_TLB_CNTL,  in cayman_pcie_gart_enable()
1273 	WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |  in cayman_pcie_gart_enable()
1279 	WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);  in cayman_pcie_gart_enable()
1280 	WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |  in cayman_pcie_gart_enable()
1284 	WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);  in cayman_pcie_gart_enable()
1285 	WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);  in cayman_pcie_gart_enable()
1286 	WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);  in cayman_pcie_gart_enable()
1287 	WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,  in cayman_pcie_gart_enable()
1289 	WREG32(VM_CONTEXT0_CNTL2, 0);  in cayman_pcie_gart_enable()
1290 	WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |  in cayman_pcie_gart_enable()
1293 	WREG32(0x15D4, 0);  in cayman_pcie_gart_enable()
1294 	WREG32(0x15D8, 0);  in cayman_pcie_gart_enable()
1295 	WREG32(0x15DC, 0);  in cayman_pcie_gart_enable()
1303 		WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);  in cayman_pcie_gart_enable()
1304 		WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2),  in cayman_pcie_gart_enable()
1306 		WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),  in cayman_pcie_gart_enable()
1311 	WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,  in cayman_pcie_gart_enable()
1313 	WREG32(VM_CONTEXT1_CNTL2, 4);  in cayman_pcie_gart_enable()
1314 	WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |  in cayman_pcie_gart_enable()
1347 	WREG32(VM_CONTEXT0_CNTL, 0);  in cayman_pcie_gart_disable()
1348 	WREG32(VM_CONTEXT1_CNTL, 0);  in cayman_pcie_gart_disable()
1350 	WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |  in cayman_pcie_gart_disable()
1354 	WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |  in cayman_pcie_gart_disable()
1358 	WREG32(VM_L2_CNTL2, 0);  in cayman_pcie_gart_disable()
1359 	WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |  in cayman_pcie_gart_disable()
1376 	WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));  in cayman_cp_int_cntl_setup()
1377 	WREG32(CP_INT_CNTL, cp_int_cntl);  in cayman_cp_int_cntl_setup()
1445 		WREG32(CP_ME_CNTL, 0);  in cayman_cp_enable()
1449 		WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));  in cayman_cp_enable()
1450 		WREG32(SCRATCH_UMSK, 0);  in cayman_cp_enable()
1493 		WREG32(CP_RB0_WPTR, ring->wptr);  in cayman_gfx_set_wptr()
1496 		WREG32(CP_RB1_WPTR, ring->wptr);  in cayman_gfx_set_wptr()
1499 		WREG32(CP_RB2_WPTR, ring->wptr);  in cayman_gfx_set_wptr()
1515 	WREG32(CP_PFP_UCODE_ADDR, 0);  in cayman_cp_load_microcode()
1517 		WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));  in cayman_cp_load_microcode()
1518 	WREG32(CP_PFP_UCODE_ADDR, 0);  in cayman_cp_load_microcode()
1521 	WREG32(CP_ME_RAM_WADDR, 0);  in cayman_cp_load_microcode()
1523 		WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));  in cayman_cp_load_microcode()
1525 	WREG32(CP_PFP_UCODE_ADDR, 0);  in cayman_cp_load_microcode()
1526 	WREG32(CP_ME_RAM_WADDR, 0);  in cayman_cp_load_microcode()
1527 	WREG32(CP_ME_RAM_RADDR, 0);  in cayman_cp_load_microcode()
1646 	WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |  in cayman_cp_resume()
1654 	WREG32(GRBM_SOFT_RESET, 0);  in cayman_cp_resume()
1657 	WREG32(CP_SEM_WAIT_TIMER, 0x0);  in cayman_cp_resume()
1658 	WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);  in cayman_cp_resume()
1661 	WREG32(CP_RB_WPTR_DELAY, 0);  in cayman_cp_resume()
1663 	WREG32(CP_DEBUG, (1 << 27));  in cayman_cp_resume()
1666 	WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);  in cayman_cp_resume()
1667 	WREG32(SCRATCH_UMSK, 0xff);  in cayman_cp_resume()
1680 		WREG32(cp_rb_cntl[i], rb_cntl);  in cayman_cp_resume()
1684 		WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);  in cayman_cp_resume()
1685 		WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);  in cayman_cp_resume()
1691 		WREG32(cp_rb_base[i], ring->gpu_addr >> 8);  in cayman_cp_resume()
1700 		WREG32(cp_rb_rptr[i], 0);  in cayman_cp_resume()
1701 		WREG32(cp_rb_wptr[i], ring->wptr);  in cayman_cp_resume()
1827 	WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);  in cayman_gpu_soft_reset()
1833 		WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);  in cayman_gpu_soft_reset()
1840 		WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);  in cayman_gpu_soft_reset()
1904 		WREG32(GRBM_SOFT_RESET, tmp);  in cayman_gpu_soft_reset()
1910 		WREG32(GRBM_SOFT_RESET, tmp);  in cayman_gpu_soft_reset()
1918 		WREG32(SRBM_SOFT_RESET, tmp);  in cayman_gpu_soft_reset()
1924 		WREG32(SRBM_SOFT_RESET, tmp);  in cayman_gpu_soft_reset()