1729 	u32 reset_mask = 0;  in cayman_gpu_check_soft_reset()  local
1740 		reset_mask |= RADEON_RESET_GFX;  in cayman_gpu_check_soft_reset()
1744 		reset_mask |= RADEON_RESET_CP;  in cayman_gpu_check_soft_reset()
1747 		reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;  in cayman_gpu_check_soft_reset()
1752 		reset_mask |= RADEON_RESET_DMA;  in cayman_gpu_check_soft_reset()
1757 		reset_mask |= RADEON_RESET_DMA1;  in cayman_gpu_check_soft_reset()
1762 		reset_mask |= RADEON_RESET_DMA;  in cayman_gpu_check_soft_reset()
1765 		reset_mask |= RADEON_RESET_DMA1;  in cayman_gpu_check_soft_reset()
1770 		reset_mask |= RADEON_RESET_RLC;  in cayman_gpu_check_soft_reset()
1773 		reset_mask |= RADEON_RESET_IH;  in cayman_gpu_check_soft_reset()
1776 		reset_mask |= RADEON_RESET_SEM;  in cayman_gpu_check_soft_reset()
1779 		reset_mask |= RADEON_RESET_GRBM;  in cayman_gpu_check_soft_reset()
1782 		reset_mask |= RADEON_RESET_VMC;  in cayman_gpu_check_soft_reset()
1786 		reset_mask |= RADEON_RESET_MC;  in cayman_gpu_check_soft_reset()
1789 		reset_mask |= RADEON_RESET_DISPLAY;  in cayman_gpu_check_soft_reset()
1794 		reset_mask |= RADEON_RESET_VMC;  in cayman_gpu_check_soft_reset()
1797 	if (reset_mask & RADEON_RESET_MC) {  in cayman_gpu_check_soft_reset()
1798 		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);  in cayman_gpu_check_soft_reset()
1799 		reset_mask &= ~RADEON_RESET_MC;  in cayman_gpu_check_soft_reset()
1802 	return reset_mask;  in cayman_gpu_check_soft_reset()
1805 static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)  in cayman_gpu_soft_reset()  argument
1811 	if (reset_mask == 0)  in cayman_gpu_soft_reset()
1814 	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);  in cayman_gpu_soft_reset()
1829 	if (reset_mask & RADEON_RESET_DMA) {  in cayman_gpu_soft_reset()
1836 	if (reset_mask & RADEON_RESET_DMA1) {  in cayman_gpu_soft_reset()
1850 	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {  in cayman_gpu_soft_reset()
1865 	if (reset_mask & RADEON_RESET_CP) {  in cayman_gpu_soft_reset()
1871 	if (reset_mask & RADEON_RESET_DMA)  in cayman_gpu_soft_reset()
1874 	if (reset_mask & RADEON_RESET_DMA1)  in cayman_gpu_soft_reset()
1877 	if (reset_mask & RADEON_RESET_DISPLAY)  in cayman_gpu_soft_reset()
1880 	if (reset_mask & RADEON_RESET_RLC)  in cayman_gpu_soft_reset()
1883 	if (reset_mask & RADEON_RESET_SEM)  in cayman_gpu_soft_reset()
1886 	if (reset_mask & RADEON_RESET_IH)  in cayman_gpu_soft_reset()
1889 	if (reset_mask & RADEON_RESET_GRBM)  in cayman_gpu_soft_reset()
1892 	if (reset_mask & RADEON_RESET_VMC)  in cayman_gpu_soft_reset()
1896 		if (reset_mask & RADEON_RESET_MC)  in cayman_gpu_soft_reset()
1939 	u32 reset_mask;  in cayman_asic_reset()  local
1941 	reset_mask = cayman_gpu_check_soft_reset(rdev);  in cayman_asic_reset()
1943 	if (reset_mask)  in cayman_asic_reset()
1946 	cayman_gpu_soft_reset(rdev, reset_mask);  in cayman_asic_reset()
1948 	reset_mask = cayman_gpu_check_soft_reset(rdev);  in cayman_asic_reset()
1950 	if (reset_mask)  in cayman_asic_reset()
1969 	u32 reset_mask = cayman_gpu_check_soft_reset(rdev);  in cayman_gfx_is_lockup()  local
1971 	if (!(reset_mask & (RADEON_RESET_GFX |  in cayman_gfx_is_lockup()