1086 		tmp = RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK;  in ni_stop_smc()
1183 	ni_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);  in ni_read_clock_registers()
1184 	ni_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);  in ni_read_clock_registers()
1185 	ni_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);  in ni_read_clock_registers()
1186 	ni_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);  in ni_read_clock_registers()
1187 	ni_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);  in ni_read_clock_registers()
1188 	ni_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);  in ni_read_clock_registers()
1189 	ni_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);  in ni_read_clock_registers()
1190 	ni_pi->clock_registers.mpll_ad_func_cntl_2 = RREG32(MPLL_AD_FUNC_CNTL_2);  in ni_read_clock_registers()
1191 	ni_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);  in ni_read_clock_registers()
1192 	ni_pi->clock_registers.mpll_dq_func_cntl_2 = RREG32(MPLL_DQ_FUNC_CNTL_2);  in ni_read_clock_registers()
1193 	ni_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);  in ni_read_clock_registers()
1194 	ni_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);  in ni_read_clock_registers()
1195 	ni_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);  in ni_read_clock_registers()
1196 	ni_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);  in ni_read_clock_registers()
1208 		RREG32(GB_ADDR_CONFIG);
1367 	u32 tmp = RREG32(CG_CAC_CTRL) & TID_CNT_MASK;  in ni_get_smc_power_scaling_factor()
1514 		mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING);  in ni_copy_and_switch_arb_sets()
1515 		mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);  in ni_copy_and_switch_arb_sets()
1516 		burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;  in ni_copy_and_switch_arb_sets()
1519 		mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_1);  in ni_copy_and_switch_arb_sets()
1520 		mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);  in ni_copy_and_switch_arb_sets()
1521 		burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;  in ni_copy_and_switch_arb_sets()
1524 		mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_2);  in ni_copy_and_switch_arb_sets()
1525 		mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);  in ni_copy_and_switch_arb_sets()
1526 		burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;  in ni_copy_and_switch_arb_sets()
1529 		mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_3);  in ni_copy_and_switch_arb_sets()
1530 		mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);  in ni_copy_and_switch_arb_sets()
1531 		burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;  in ni_copy_and_switch_arb_sets()
1562 	mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;  in ni_copy_and_switch_arb_sets()
1628 	dram_timing = RREG32(MC_ARB_DRAM_TIMING);  in ni_populate_memory_timing_parameters()
1629 	dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);  in ni_populate_memory_timing_parameters()
2189 		mc_seq_misc7 = RREG32(MC_SEQ_MISC7);  in ni_populate_mclk_value()
2319 	u32 tmp = RREG32(DC_STUTTER_CNTL);  in ni_convert_power_level_to_smc()
2346 			    ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))  in ni_convert_power_level_to_smc()
2347 				dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;  in ni_convert_power_level_to_smc()
2349 				dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;  in ni_convert_power_level_to_smc()
2721 			temp_reg = RREG32(MC_PMG_CMD_EMRS);  in ni_set_mc_special_registers()
2732 			temp_reg = RREG32(MC_PMG_CMD_MRS);  in ni_set_mc_special_registers()
2747 			temp_reg = RREG32(MC_PMG_CMD_MRS1);  in ni_set_mc_special_registers()
2883 	WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));  in ni_initialize_mc_reg_table()
2884 	WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));  in ni_initialize_mc_reg_table()
2885 	WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));  in ni_initialize_mc_reg_table()
2886 	WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));  in ni_initialize_mc_reg_table()
2887 	WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));  in ni_initialize_mc_reg_table()
2888 	WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));  in ni_initialize_mc_reg_table()
2889 	WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));  in ni_initialize_mc_reg_table()
2890 	WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));  in ni_initialize_mc_reg_table()
2891 	WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));  in ni_initialize_mc_reg_table()
2892 	WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));  in ni_initialize_mc_reg_table()
2893 	WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));  in ni_initialize_mc_reg_table()
2894 	WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));  in ni_initialize_mc_reg_table()
2895 	WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));  in ni_initialize_mc_reg_table()
3154 	reg = RREG32(CG_CAC_CTRL) & ~(TID_CNT_MASK | TID_UNIT_MASK);  in ni_initialize_smc_cac_tables()
3354 	reg = RREG32(SQ_CAC_THRESHOLD) & ~(VSP_MASK |  in ni_initialize_hardware_cac_manager()
3470 				bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;  in ni_enable_bif_dynamic_pcie_gen2()
3485 				bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;  in ni_enable_bif_dynamic_pcie_gen2()
4309 		(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>  in ni_dpm_debugfs_print_current_performance_level()
4329 		(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>  in ni_dpm_get_current_sclk()
4347 		(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>  in ni_dpm_get_current_mclk()