1295 		p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;  in r100_reloc_pitch_offset()
1297 		p->ib.ptr[idx] = (value & 0xffc00000) | tmp;  in r100_reloc_pitch_offset()
1309 	volatile uint32_t *ib;  in r100_packet3_load_vbpntr()  local
1312 	ib = p->ib.ptr;  in r100_packet3_load_vbpntr()
1331 		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);  in r100_packet3_load_vbpntr()
1343 		ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);  in r100_packet3_load_vbpntr()
1357 		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);  in r100_packet3_load_vbpntr()
1432 	volatile uint32_t *ib;  in r100_cs_packet_parse_vline()  local
1434 	ib = p->ib.ptr;  in r100_cs_packet_parse_vline()
1475 		ib[h_idx + 2] = PACKET2(0);  in r100_cs_packet_parse_vline()
1476 		ib[h_idx + 3] = PACKET2(0);  in r100_cs_packet_parse_vline()
1491 		ib[h_idx] = header;  in r100_cs_packet_parse_vline()
1492 		ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;  in r100_cs_packet_parse_vline()
1557 	volatile uint32_t *ib;  in r100_packet0_check()  local
1564 	ib = p->ib.ptr;  in r100_packet0_check()
1598 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1611 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1632 			ib[idx] = tmp + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1634 			ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1652 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1670 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1688 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1713 			ib[idx] = tmp;  in r100_packet0_check()
1715 			ib[idx] = idx_value;  in r100_packet0_check()
1776 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1917 	volatile uint32_t *ib;  in r100_packet3_check()  local
1920 	ib = p->ib.ptr;  in r100_packet3_check()
1936 		ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);  in r100_packet3_check()
1950 		ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);  in r100_packet3_check()
3676 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)  in r100_ring_ib_execute()  argument
3687 	radeon_ring_write(ring, ib->gpu_addr);  in r100_ring_ib_execute()
3688 	radeon_ring_write(ring, ib->length_dw);  in r100_ring_ib_execute()
3693 	struct radeon_ib ib;  in r100_ib_test()  local
3705 	r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);  in r100_ib_test()
3710 	ib.ptr[0] = PACKET0(scratch, 0);  in r100_ib_test()
3711 	ib.ptr[1] = 0xDEADBEEF;  in r100_ib_test()
3712 	ib.ptr[2] = PACKET2(0);  in r100_ib_test()
3713 	ib.ptr[3] = PACKET2(0);  in r100_ib_test()
3714 	ib.ptr[4] = PACKET2(0);  in r100_ib_test()
3715 	ib.ptr[5] = PACKET2(0);  in r100_ib_test()
3716 	ib.ptr[6] = PACKET2(0);  in r100_ib_test()
3717 	ib.ptr[7] = PACKET2(0);  in r100_ib_test()
3718 	ib.length_dw = 8;  in r100_ib_test()
3719 	r = radeon_ib_schedule(rdev, &ib, NULL, false);  in r100_ib_test()
3724 	r = radeon_fence_wait(ib.fence, false);  in r100_ib_test()
3744 	radeon_ib_free(rdev, &ib);  in r100_ib_test()