Lines Matching refs:idx_value
1310 u32 idx_value; in r100_packet3_load_vbpntr() local
1330 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
1333 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()
1345 track->arrays[i + 1].esize = idx_value >> 24; in r100_packet3_load_vbpntr()
1356 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
1359 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()
1562 u32 idx_value; in r100_packet0_check() local
1567 idx_value = radeon_get_ib_value(p, idx); in r100_packet0_check()
1596 track->zb.offset = idx_value; in r100_packet0_check()
1598 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1609 track->cb[0].offset = idx_value; in r100_packet0_check()
1611 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1630 tmp = idx_value & ~(0x7 << 2); in r100_packet0_check()
1634 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1651 track->textures[0].cube_info[i].offset = idx_value; in r100_packet0_check()
1652 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1669 track->textures[1].cube_info[i].offset = idx_value; in r100_packet0_check()
1670 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1687 track->textures[2].cube_info[i].offset = idx_value; in r100_packet0_check()
1688 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1693 track->maxy = ((idx_value >> 16) & 0x7FF); in r100_packet0_check()
1711 tmp = idx_value & ~(0x7 << 16); in r100_packet0_check()
1715 ib[idx] = idx_value; in r100_packet0_check()
1717 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; in r100_packet0_check()
1721 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; in r100_packet0_check()
1725 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { in r100_packet0_check()
1743 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); in r100_packet0_check()
1746 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); in r100_packet0_check()
1751 switch (idx_value & 0xf) { in r100_packet0_check()
1776 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1780 uint32_t temp = idx_value >> 4; in r100_packet0_check()
1787 track->vap_vf_cntl = idx_value; in r100_packet0_check()
1790 track->vtx_size = r100_get_vtx_size(idx_value); in r100_packet0_check()
1796 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; in r100_packet0_check()
1797 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; in r100_packet0_check()
1804 track->textures[i].pitch = idx_value + 32; in r100_packet0_check()
1811 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) in r100_packet0_check()
1813 tmp = (idx_value >> 23) & 0x7; in r100_packet0_check()
1816 tmp = (idx_value >> 27) & 0x7; in r100_packet0_check()
1825 if (idx_value & RADEON_TXFORMAT_NON_POWER2) { in r100_packet0_check()
1829 …track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDT… in r100_packet0_check()
1830 …track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HE… in r100_packet0_check()
1832 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) in r100_packet0_check()
1834 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { in r100_packet0_check()
1870 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); in r100_packet0_check()
1871 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); in r100_packet0_check()
1877 tmp = idx_value; in r100_packet0_check()