59 	uint32_t tmp;  in rv370_pcie_gart_tlb_flush()  local
64 		tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);  in rv370_pcie_gart_tlb_flush()
65 		WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);  in rv370_pcie_gart_tlb_flush()
67 		WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);  in rv370_pcie_gart_tlb_flush()
125 	uint32_t tmp;  in rv370_pcie_gart_enable()  local
136 	tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;  in rv370_pcie_gart_enable()
137 	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);  in rv370_pcie_gart_enable()
139 	tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;  in rv370_pcie_gart_enable()
140 	WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);  in rv370_pcie_gart_enable()
150 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);  in rv370_pcie_gart_enable()
151 	tmp |= RADEON_PCIE_TX_GART_EN;  in rv370_pcie_gart_enable()
152 	tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;  in rv370_pcie_gart_enable()
153 	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);  in rv370_pcie_gart_enable()
164 	u32 tmp;  in rv370_pcie_gart_disable()  local
170 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);  in rv370_pcie_gart_disable()
171 	tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;  in rv370_pcie_gart_disable()
172 	WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);  in rv370_pcie_gart_disable()
320 	uint32_t tmp;  in r300_mc_wait_for_idle()  local
324 		tmp = RREG32(RADEON_MC_STATUS);  in r300_mc_wait_for_idle()
325 		if (tmp & R300_MC_IDLE) {  in r300_mc_wait_for_idle()
335 	uint32_t gb_tile_config, tmp;  in r300_gpu_init()  local
369 	tmp = RREG32(R300_DST_PIPE_CONFIG);  in r300_gpu_init()
370 	WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);  in r300_gpu_init()
391 	u32 status, tmp;  in r300_asic_reset()  local
403 	tmp = RREG32(RADEON_CP_RB_CNTL);  in r300_asic_reset()
404 	WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);  in r300_asic_reset()
407 	WREG32(RADEON_CP_RB_CNTL, tmp);  in r300_asic_reset()
451 	u32 tmp;  in r300_mc_init()  local
455 	tmp = RREG32(RADEON_MEM_CNTL);  in r300_mc_init()
456 	tmp &= R300_MEM_NUM_CHANNELS_MASK;  in r300_mc_init()
457 	switch (tmp) {  in r300_mc_init()
570 	uint32_t tmp;  in rv370_debugfs_pcie_gart_info()  local
572 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);  in rv370_debugfs_pcie_gart_info()
573 	seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);  in rv370_debugfs_pcie_gart_info()
574 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);  in rv370_debugfs_pcie_gart_info()
575 	seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);  in rv370_debugfs_pcie_gart_info()
576 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);  in rv370_debugfs_pcie_gart_info()
577 	seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);  in rv370_debugfs_pcie_gart_info()
578 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);  in rv370_debugfs_pcie_gart_info()
579 	seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);  in rv370_debugfs_pcie_gart_info()
580 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);  in rv370_debugfs_pcie_gart_info()
581 	seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);  in rv370_debugfs_pcie_gart_info()
582 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);  in rv370_debugfs_pcie_gart_info()
583 	seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);  in rv370_debugfs_pcie_gart_info()
584 	tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);  in rv370_debugfs_pcie_gart_info()
585 	seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);  in rv370_debugfs_pcie_gart_info()
610 	uint32_t tmp, tile_flags = 0;  in r300_packet0_check()  local
702 			tmp = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
703 			tmp |= tile_flags;  in r300_packet0_check()
704 			ib[idx] = tmp;  in r300_packet0_check()
771 			tmp = idx_value & ~(0x7 << 16);  in r300_packet0_check()
772 			tmp |= tile_flags;  in r300_packet0_check()
773 			ib[idx] = tmp;  in r300_packet0_check()
856 			tmp = idx_value & ~(0x7 << 16);  in r300_packet0_check()
857 			tmp |= tile_flags;  in r300_packet0_check()
858 			ib[idx] = tmp;  in r300_packet0_check()
891 		tmp = (idx_value >> 25) & 0x3;  in r300_packet0_check()
892 		track->textures[i].tex_coord_type = tmp;  in r300_packet0_check()
977 		tmp = idx_value & 0x7;  in r300_packet0_check()
978 		if (tmp == 2 || tmp == 4 || tmp == 6) {  in r300_packet0_check()
981 		tmp = (idx_value >> 3) & 0x7;  in r300_packet0_check()
982 		if (tmp == 2 || tmp == 4 || tmp == 6) {  in r300_packet0_check()
1005 		tmp = idx_value & 0x3FFF;  in r300_packet0_check()
1006 		track->textures[i].pitch = tmp + 1;  in r300_packet0_check()
1008 			tmp = ((idx_value >> 15) & 1) << 11;  in r300_packet0_check()
1009 			track->textures[i].width_11 = tmp;  in r300_packet0_check()
1010 			tmp = ((idx_value >> 16) & 1) << 11;  in r300_packet0_check()
1011 			track->textures[i].height_11 = tmp;  in r300_packet0_check()
1043 		tmp = idx_value & 0x7FF;  in r300_packet0_check()
1044 		track->textures[i].width = tmp + 1;  in r300_packet0_check()
1045 		tmp = (idx_value >> 11) & 0x7FF;  in r300_packet0_check()
1046 		track->textures[i].height = tmp + 1;  in r300_packet0_check()
1047 		tmp = (idx_value >> 26) & 0xF;  in r300_packet0_check()
1048 		track->textures[i].num_levels = tmp;  in r300_packet0_check()
1049 		tmp = idx_value & (1 << 31);  in r300_packet0_check()
1050 		track->textures[i].use_pitch = !!tmp;  in r300_packet0_check()
1051 		tmp = (idx_value >> 22) & 0xF;  in r300_packet0_check()
1052 		track->textures[i].txdepth = tmp;  in r300_packet0_check()
1338 	u32 tmp;  in r300_clock_startup()  local
1343 	tmp = RREG32_PLL(R_00000D_SCLK_CNTL);  in r300_clock_startup()
1344 	tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);  in r300_clock_startup()
1346 		tmp |= S_00000D_FORCE_VAP(1);  in r300_clock_startup()
1347 	WREG32_PLL(R_00000D_SCLK_CNTL, tmp);  in r300_clock_startup()