Lines Matching refs:RREG32
312 (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) { in r300_errata()
324 tmp = RREG32(RADEON_MC_STATUS); in r300_mc_wait_for_idle()
369 tmp = RREG32(R300_DST_PIPE_CONFIG); in r300_gpu_init()
394 status = RREG32(R_000E40_RBBM_STATUS); in r300_asic_reset()
399 status = RREG32(R_000E40_RBBM_STATUS); in r300_asic_reset()
403 tmp = RREG32(RADEON_CP_RB_CNTL); in r300_asic_reset()
414 RREG32(R_0000F0_RBBM_SOFT_RESET); in r300_asic_reset()
418 status = RREG32(R_000E40_RBBM_STATUS); in r300_asic_reset()
426 RREG32(R_0000F0_RBBM_SOFT_RESET); in r300_asic_reset()
430 status = RREG32(R_000E40_RBBM_STATUS); in r300_asic_reset()
455 tmp = RREG32(RADEON_MEM_CNTL); in r300_mc_init()
466 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; in r300_mc_init()
1400 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r300_startup()
1431 RREG32(R_000E40_RBBM_STATUS), in r300_resume()
1432 RREG32(R_0007C0_CP_STAT)); in r300_resume()
1512 RREG32(R_000E40_RBBM_STATUS), in r300_init()
1513 RREG32(R_0007C0_CP_STAT)); in r300_init()