219 	unsigned gb_tile_config;  in r300_ring_start()  local
223 	gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);  in r300_ring_start()
226 		gb_tile_config |= R300_PIPE_COUNT_R300;  in r300_ring_start()
229 		gb_tile_config |= R300_PIPE_COUNT_R420_3P;  in r300_ring_start()
232 		gb_tile_config |= R300_PIPE_COUNT_R420;  in r300_ring_start()
236 		gb_tile_config |= R300_PIPE_COUNT_RV350;  in r300_ring_start()
251 	radeon_ring_write(ring, gb_tile_config);  in r300_ring_start()
335 	uint32_t gb_tile_config, tmp;  in r300_gpu_init()  local
346 	gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);  in r300_gpu_init()
349 		gb_tile_config |= R300_PIPE_COUNT_R300;  in r300_gpu_init()
352 		gb_tile_config |= R300_PIPE_COUNT_R420_3P;  in r300_gpu_init()
355 		gb_tile_config |= R300_PIPE_COUNT_R420;  in r300_gpu_init()
359 		gb_tile_config |= R300_PIPE_COUNT_RV350;  in r300_gpu_init()
362 	WREG32(R300_GB_TILE_CONFIG, gb_tile_config);  in r300_gpu_init()