613 	u32 idx_value;  in r300_packet0_check()  local
617 	idx_value = radeon_get_ib_value(p, idx);  in r300_packet0_check()
649 		track->cb[i].offset = idx_value;  in r300_packet0_check()
651 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
662 		track->zb.offset = idx_value;  in r300_packet0_check()
664 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
692 			ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */  in r300_packet0_check()
693 				  ((idx_value & ~31) + (u32)reloc->gpu_offset);  in r300_packet0_check()
702 			tmp = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
712 		track->vap_vf_cntl = idx_value;  in r300_packet0_check()
716 		track->vtx_size = idx_value & 0x7F;  in r300_packet0_check()
720 		track->max_indx = idx_value & 0x00FFFFFFUL;  in r300_packet0_check()
726 		track->vap_alt_nverts = idx_value & 0xFFFFFF;  in r300_packet0_check()
730 		track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;  in r300_packet0_check()
739 		if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */  in r300_packet0_check()
744 		track->num_cb = ((idx_value >> 5) & 0x3) + 1;  in r300_packet0_check()
771 			tmp = idx_value & ~(0x7 << 16);  in r300_packet0_check()
776 		track->cb[i].pitch = idx_value & 0x3FFE;  in r300_packet0_check()
777 		switch (((idx_value >> 21) & 0xF)) {  in r300_packet0_check()
792 					  ((idx_value >> 21) & 0xF));  in r300_packet0_check()
807 				  ((idx_value >> 21) & 0xF));  in r300_packet0_check()
814 		if (idx_value & 2) {  in r300_packet0_check()
823 		switch ((idx_value & 0xF)) {  in r300_packet0_check()
833 				  (idx_value & 0xF));  in r300_packet0_check()
856 			tmp = idx_value & ~(0x7 << 16);  in r300_packet0_check()
860 		track->zb.pitch = idx_value & 0x3FFC;  in r300_packet0_check()
868 			enabled = !!(idx_value & (1 << i));  in r300_packet0_check()
891 		tmp = (idx_value >> 25) & 0x3;  in r300_packet0_check()
893 		switch ((idx_value & 0x1F)) {  in r300_packet0_check()
942 					  (idx_value & 0x1F));  in r300_packet0_check()
954 				  (idx_value & 0x1F));  in r300_packet0_check()
977 		tmp = idx_value & 0x7;  in r300_packet0_check()
981 		tmp = (idx_value >> 3) & 0x7;  in r300_packet0_check()
1005 		tmp = idx_value & 0x3FFF;  in r300_packet0_check()
1008 			tmp = ((idx_value >> 15) & 1) << 11;  in r300_packet0_check()
1010 			tmp = ((idx_value >> 16) & 1) << 11;  in r300_packet0_check()
1014 			if (idx_value & (1 << 14)) {  in r300_packet0_check()
1019 		} else if (idx_value & (1 << 14)) {  in r300_packet0_check()
1043 		tmp = idx_value & 0x7FF;  in r300_packet0_check()
1045 		tmp = (idx_value >> 11) & 0x7FF;  in r300_packet0_check()
1047 		tmp = (idx_value >> 26) & 0xF;  in r300_packet0_check()
1049 		tmp = idx_value & (1 << 31);  in r300_packet0_check()
1051 		tmp = (idx_value >> 22) & 0xF;  in r300_packet0_check()
1063 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
1067 		track->color_channel_mask = idx_value;  in r300_packet0_check()
1075 			if (idx_value & 0x1)  in r300_packet0_check()
1076 				ib[idx] = idx_value & ~1;  in r300_packet0_check()
1081 		track->zb_cb_clear = !!(idx_value & (1 << 5));  in r300_packet0_check()
1085 			if (idx_value & (R300_HIZ_ENABLE |  in r300_packet0_check()
1094 		track->blend_read_enable = !!(idx_value & (1 << 2));  in r300_packet0_check()
1106 		track->aa.offset = idx_value;  in r300_packet0_check()
1108 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
1111 		track->aa.pitch = idx_value & 0x3FFE;  in r300_packet0_check()
1115 		track->aaresolve = idx_value & 0x1;  in r300_packet0_check()
1122 		if (idx_value && (p->rdev->hyperz_filp != p->filp))  in r300_packet0_check()
1126 		if (idx_value && (p->rdev->hyperz_filp != p->filp))  in r300_packet0_check()
1144 	       reg, idx, idx_value);  in r300_packet0_check()