Lines Matching refs:mc
138 WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start); in rv370_pcie_gart_enable()
139 tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK; in rv370_pcie_gart_enable()
146 WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start); in rv370_pcie_gart_enable()
156 (unsigned)(rdev->mc.gtt_size >> 20), in rv370_pcie_gart_enable()
454 rdev->mc.vram_is_ddr = true; in r300_mc_init()
458 case 0: rdev->mc.vram_width = 64; break; in r300_mc_init()
459 case 1: rdev->mc.vram_width = 128; break; in r300_mc_init()
460 case 2: rdev->mc.vram_width = 256; break; in r300_mc_init()
461 default: rdev->mc.vram_width = 128; break; in r300_mc_init()
464 base = rdev->mc.aper_base; in r300_mc_init()
467 radeon_vram_location(rdev, &rdev->mc, base); in r300_mc_init()
468 rdev->mc.gtt_base_align = 0; in r300_mc_init()
470 radeon_gtt_location(rdev, &rdev->mc); in r300_mc_init()
1316 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) | in r300_mc_program()
1317 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); in r300_mc_program()
1318 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); in r300_mc_program()
1320 upper_32_bits(rdev->mc.agp_base) & 0xff); in r300_mc_program()
1331 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | in r300_mc_program()
1332 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); in r300_mc_program()