Lines Matching refs:tmp
251 u32 tmp = 0; in dce3_program_fmt() local
276 tmp |= FMT_SPATIAL_DITHER_EN; in dce3_program_fmt()
278 tmp |= FMT_TRUNCATE_EN; in dce3_program_fmt()
283 tmp |= (FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH); in dce3_program_fmt()
285 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH); in dce3_program_fmt()
293 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce3_program_fmt()
809 u32 tmp; in r600_hpd_set_polarity() local
815 tmp = RREG32(DC_HPD1_INT_CONTROL); in r600_hpd_set_polarity()
817 tmp &= ~DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
819 tmp |= DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
820 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_hpd_set_polarity()
823 tmp = RREG32(DC_HPD2_INT_CONTROL); in r600_hpd_set_polarity()
825 tmp &= ~DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
827 tmp |= DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
828 WREG32(DC_HPD2_INT_CONTROL, tmp); in r600_hpd_set_polarity()
831 tmp = RREG32(DC_HPD3_INT_CONTROL); in r600_hpd_set_polarity()
833 tmp &= ~DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
835 tmp |= DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
836 WREG32(DC_HPD3_INT_CONTROL, tmp); in r600_hpd_set_polarity()
839 tmp = RREG32(DC_HPD4_INT_CONTROL); in r600_hpd_set_polarity()
841 tmp &= ~DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
843 tmp |= DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
844 WREG32(DC_HPD4_INT_CONTROL, tmp); in r600_hpd_set_polarity()
847 tmp = RREG32(DC_HPD5_INT_CONTROL); in r600_hpd_set_polarity()
849 tmp &= ~DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
851 tmp |= DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
852 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_hpd_set_polarity()
856 tmp = RREG32(DC_HPD6_INT_CONTROL); in r600_hpd_set_polarity()
858 tmp &= ~DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
860 tmp |= DC_HPDx_INT_POLARITY; in r600_hpd_set_polarity()
861 WREG32(DC_HPD6_INT_CONTROL, tmp); in r600_hpd_set_polarity()
869 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); in r600_hpd_set_polarity()
871 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_hpd_set_polarity()
873 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_hpd_set_polarity()
874 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); in r600_hpd_set_polarity()
877 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); in r600_hpd_set_polarity()
879 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_hpd_set_polarity()
881 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_hpd_set_polarity()
882 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); in r600_hpd_set_polarity()
885 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); in r600_hpd_set_polarity()
887 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_hpd_set_polarity()
889 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_hpd_set_polarity()
890 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); in r600_hpd_set_polarity()
916 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa); in r600_hpd_init() local
918 tmp |= DC_HPDx_EN; in r600_hpd_init()
922 WREG32(DC_HPD1_CONTROL, tmp); in r600_hpd_init()
925 WREG32(DC_HPD2_CONTROL, tmp); in r600_hpd_init()
928 WREG32(DC_HPD3_CONTROL, tmp); in r600_hpd_init()
931 WREG32(DC_HPD4_CONTROL, tmp); in r600_hpd_init()
935 WREG32(DC_HPD5_CONTROL, tmp); in r600_hpd_init()
938 WREG32(DC_HPD6_CONTROL, tmp); in r600_hpd_init()
1022 u32 tmp; in r600_pcie_gart_tlb_flush() local
1028 u32 tmp; in r600_pcie_gart_tlb_flush() local
1036 tmp = readl((void __iomem *)ptr); in r600_pcie_gart_tlb_flush()
1045 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE); in r600_pcie_gart_tlb_flush()
1046 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT; in r600_pcie_gart_tlb_flush()
1047 if (tmp == 2) { in r600_pcie_gart_tlb_flush()
1051 if (tmp) { in r600_pcie_gart_tlb_flush()
1076 u32 tmp; in r600_pcie_gart_enable() local
1094 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in r600_pcie_gart_enable()
1098 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); in r600_pcie_gart_enable()
1099 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); in r600_pcie_gart_enable()
1100 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); in r600_pcie_gart_enable()
1101 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); in r600_pcie_gart_enable()
1102 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); in r600_pcie_gart_enable()
1103 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); in r600_pcie_gart_enable()
1104 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); in r600_pcie_gart_enable()
1105 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); in r600_pcie_gart_enable()
1106 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); in r600_pcie_gart_enable()
1107 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); in r600_pcie_gart_enable()
1108 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); in r600_pcie_gart_enable()
1109 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); in r600_pcie_gart_enable()
1110 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); in r600_pcie_gart_enable()
1111 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); in r600_pcie_gart_enable()
1112 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); in r600_pcie_gart_enable()
1113 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); in r600_pcie_gart_enable()
1134 u32 tmp; in r600_pcie_gart_disable() local
1146 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) | in r600_pcie_gart_disable()
1148 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); in r600_pcie_gart_disable()
1149 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); in r600_pcie_gart_disable()
1150 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); in r600_pcie_gart_disable()
1151 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); in r600_pcie_gart_disable()
1152 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); in r600_pcie_gart_disable()
1153 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); in r600_pcie_gart_disable()
1154 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); in r600_pcie_gart_disable()
1155 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); in r600_pcie_gart_disable()
1156 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); in r600_pcie_gart_disable()
1157 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); in r600_pcie_gart_disable()
1158 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); in r600_pcie_gart_disable()
1159 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); in r600_pcie_gart_disable()
1160 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); in r600_pcie_gart_disable()
1161 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); in r600_pcie_gart_disable()
1162 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); in r600_pcie_gart_disable()
1163 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); in r600_pcie_gart_disable()
1176 u32 tmp; in r600_agp_enable() local
1186 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | in r600_agp_enable()
1190 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); in r600_agp_enable()
1191 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); in r600_agp_enable()
1192 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); in r600_agp_enable()
1193 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); in r600_agp_enable()
1194 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); in r600_agp_enable()
1195 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); in r600_agp_enable()
1196 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); in r600_agp_enable()
1197 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); in r600_agp_enable()
1198 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); in r600_agp_enable()
1199 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); in r600_agp_enable()
1200 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); in r600_agp_enable()
1201 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); in r600_agp_enable()
1202 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); in r600_agp_enable()
1203 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); in r600_agp_enable()
1211 u32 tmp; in r600_mc_wait_for_idle() local
1215 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00; in r600_mc_wait_for_idle()
1216 if (!tmp) in r600_mc_wait_for_idle()
1251 u32 tmp; in r600_mc_program() local
1290 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in r600_mc_program()
1291 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in r600_mc_program()
1292 WREG32(MC_VM_FB_LOCATION, tmp); in r600_mc_program()
1381 u32 tmp; in r600_mc_init() local
1388 tmp = RREG32(RAMCFG); in r600_mc_init()
1389 if (tmp & CHANSIZE_OVERRIDE) { in r600_mc_init()
1391 } else if (tmp & CHANSIZE_MASK) { in r600_mc_init()
1396 tmp = RREG32(CHMAP); in r600_mc_init()
1397 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { in r600_mc_init()
1502 u32 tmp = RREG32(R600_BIOS_3_SCRATCH); in r600_set_bios_scratch_engine_hung() local
1505 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; in r600_set_bios_scratch_engine_hung()
1507 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; in r600_set_bios_scratch_engine_hung()
1509 WREG32(R600_BIOS_3_SCRATCH, tmp); in r600_set_bios_scratch_engine_hung()
1536 u32 i, j, tmp; in r600_is_display_hung() local
1548 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in r600_is_display_hung()
1549 if (tmp != crtc_status[i]) in r600_is_display_hung()
1564 u32 tmp; in r600_gpu_check_soft_reset() local
1567 tmp = RREG32(R_008010_GRBM_STATUS); in r600_gpu_check_soft_reset()
1569 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | in r600_gpu_check_soft_reset()
1570 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | in r600_gpu_check_soft_reset()
1571 G_008010_TA_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | in r600_gpu_check_soft_reset()
1572 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | in r600_gpu_check_soft_reset()
1573 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) in r600_gpu_check_soft_reset()
1576 if (G_008010_PA_BUSY(tmp) | G_008010_SC_BUSY(tmp) | in r600_gpu_check_soft_reset()
1577 G_008010_SH_BUSY(tmp) | G_008010_SX_BUSY(tmp) | in r600_gpu_check_soft_reset()
1578 G_008010_TA03_BUSY(tmp) | G_008010_VGT_BUSY(tmp) | in r600_gpu_check_soft_reset()
1579 G_008010_DB03_BUSY(tmp) | G_008010_CB03_BUSY(tmp) | in r600_gpu_check_soft_reset()
1580 G_008010_SPI03_BUSY(tmp) | G_008010_VGT_BUSY_NO_DMA(tmp)) in r600_gpu_check_soft_reset()
1584 if (G_008010_CF_RQ_PENDING(tmp) | G_008010_PF_RQ_PENDING(tmp) | in r600_gpu_check_soft_reset()
1585 G_008010_CP_BUSY(tmp) | G_008010_CP_COHERENCY_BUSY(tmp)) in r600_gpu_check_soft_reset()
1588 if (G_008010_GRBM_EE_BUSY(tmp)) in r600_gpu_check_soft_reset()
1592 tmp = RREG32(DMA_STATUS_REG); in r600_gpu_check_soft_reset()
1593 if (!(tmp & DMA_IDLE)) in r600_gpu_check_soft_reset()
1597 tmp = RREG32(R_000E50_SRBM_STATUS); in r600_gpu_check_soft_reset()
1598 if (G_000E50_RLC_RQ_PENDING(tmp) | G_000E50_RLC_BUSY(tmp)) in r600_gpu_check_soft_reset()
1601 if (G_000E50_IH_BUSY(tmp)) in r600_gpu_check_soft_reset()
1604 if (G_000E50_SEM_BUSY(tmp)) in r600_gpu_check_soft_reset()
1607 if (G_000E50_GRBM_RQ_PENDING(tmp)) in r600_gpu_check_soft_reset()
1610 if (G_000E50_VMC_BUSY(tmp)) in r600_gpu_check_soft_reset()
1613 if (G_000E50_MCB_BUSY(tmp) | G_000E50_MCDZ_BUSY(tmp) | in r600_gpu_check_soft_reset()
1614 G_000E50_MCDY_BUSY(tmp) | G_000E50_MCDX_BUSY(tmp) | in r600_gpu_check_soft_reset()
1615 G_000E50_MCDW_BUSY(tmp)) in r600_gpu_check_soft_reset()
1634 u32 tmp; in r600_gpu_soft_reset() local
1654 tmp = RREG32(DMA_RB_CNTL); in r600_gpu_soft_reset()
1655 tmp &= ~DMA_RB_ENABLE; in r600_gpu_soft_reset()
1656 WREG32(DMA_RB_CNTL, tmp); in r600_gpu_soft_reset()
1730 tmp = RREG32(R_008020_GRBM_SOFT_RESET); in r600_gpu_soft_reset()
1731 tmp |= grbm_soft_reset; in r600_gpu_soft_reset()
1732 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp); in r600_gpu_soft_reset()
1733 WREG32(R_008020_GRBM_SOFT_RESET, tmp); in r600_gpu_soft_reset()
1734 tmp = RREG32(R_008020_GRBM_SOFT_RESET); in r600_gpu_soft_reset()
1738 tmp &= ~grbm_soft_reset; in r600_gpu_soft_reset()
1739 WREG32(R_008020_GRBM_SOFT_RESET, tmp); in r600_gpu_soft_reset()
1740 tmp = RREG32(R_008020_GRBM_SOFT_RESET); in r600_gpu_soft_reset()
1744 tmp = RREG32(SRBM_SOFT_RESET); in r600_gpu_soft_reset()
1745 tmp |= srbm_soft_reset; in r600_gpu_soft_reset()
1746 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in r600_gpu_soft_reset()
1747 WREG32(SRBM_SOFT_RESET, tmp); in r600_gpu_soft_reset()
1748 tmp = RREG32(SRBM_SOFT_RESET); in r600_gpu_soft_reset()
1752 tmp &= ~srbm_soft_reset; in r600_gpu_soft_reset()
1753 WREG32(SRBM_SOFT_RESET, tmp); in r600_gpu_soft_reset()
1754 tmp = RREG32(SRBM_SOFT_RESET); in r600_gpu_soft_reset()
1769 u32 tmp, i; in r600_gpu_pci_config_reset() local
1785 tmp = RREG32(DMA_RB_CNTL); in r600_gpu_pci_config_reset()
1786 tmp &= ~DMA_RB_ENABLE; in r600_gpu_pci_config_reset()
1787 WREG32(DMA_RB_CNTL, tmp); in r600_gpu_pci_config_reset()
1803 tmp = RREG32(BUS_CNTL); in r600_gpu_pci_config_reset()
1804 tmp |= VGA_COHE_SPEC_TIMER_DIS; in r600_gpu_pci_config_reset()
1805 WREG32(BUS_CNTL, tmp); in r600_gpu_pci_config_reset()
1807 tmp = RREG32(BIF_SCRATCH0); in r600_gpu_pci_config_reset()
1814 tmp = SOFT_RESET_BIF; in r600_gpu_pci_config_reset()
1815 WREG32(SRBM_SOFT_RESET, tmp); in r600_gpu_pci_config_reset()
1882 u32 pipe_rb_ratio, pipe_rb_remain, tmp; in r6xx_remap_render_backend() local
1887 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff); in r6xx_remap_render_backend()
1889 if ((tmp & 0xff) != 0xff) in r6xx_remap_render_backend()
1890 disabled_rb_mask = tmp; in r6xx_remap_render_backend()
1935 u32 tmp; in r600_gpu_init() local
2050 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT; in r600_gpu_init()
2051 if (tmp > 3) { in r600_gpu_init()
2055 tiling_config |= ROW_TILING(tmp); in r600_gpu_init()
2056 tiling_config |= SAMPLE_SPLIT(tmp); in r600_gpu_init()
2061 tmp = rdev->config.r600.max_simds - in r600_gpu_init()
2063 rdev->config.r600.active_simds = tmp; in r600_gpu_init()
2066 tmp = 0; in r600_gpu_init()
2068 tmp |= (1 << i); in r600_gpu_init()
2070 if ((disabled_rb_mask & tmp) == tmp) { in r600_gpu_init()
2074 tmp = (tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT; in r600_gpu_init()
2075 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, in r600_gpu_init()
2077 tiling_config |= tmp << 16; in r600_gpu_init()
2078 rdev->config.r600.backend_map = tmp; in r600_gpu_init()
2086 …tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >>… in r600_gpu_init()
2087 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); in r600_gpu_init()
2088 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); in r600_gpu_init()
2100 tmp = RREG32(SX_DEBUG_1); in r600_gpu_init()
2101 tmp |= SMX_EVENT_RELEASE; in r600_gpu_init()
2103 tmp |= ENABLE_NEW_SMX_ADDRESS; in r600_gpu_init()
2104 WREG32(SX_DEBUG_1, tmp); in r600_gpu_init()
2125 tmp = RREG32(SQ_MS_FIFO_SIZES); in r600_gpu_init()
2130 tmp = (CACHE_FIFO_SIZE(0xa) | in r600_gpu_init()
2136 tmp &= ~DONE_FIFO_HIWATER(0xff); in r600_gpu_init()
2137 tmp |= DONE_FIFO_HIWATER(0x4); in r600_gpu_init()
2139 WREG32(SQ_MS_FIFO_SIZES, tmp); in r600_gpu_init()
2254 tmp = rdev->config.r600.max_pipes * 16; in r600_gpu_init()
2260 tmp += 32; in r600_gpu_init()
2263 tmp += 128; in r600_gpu_init()
2268 if (tmp > 256) { in r600_gpu_init()
2269 tmp = 256; in r600_gpu_init()
2272 WREG32(VGT_GS_PER_ES, tmp); in r600_gpu_init()
2303 tmp = TC_L2_SIZE(8); in r600_gpu_init()
2307 tmp = TC_L2_SIZE(4); in r600_gpu_init()
2310 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT; in r600_gpu_init()
2313 tmp = TC_L2_SIZE(0); in r600_gpu_init()
2316 WREG32(TC_CNTL, tmp); in r600_gpu_init()
2318 tmp = RREG32(HDP_HOST_PATH_CNTL); in r600_gpu_init()
2319 WREG32(HDP_HOST_PATH_CNTL, tmp); in r600_gpu_init()
2321 tmp = RREG32(ARB_POP); in r600_gpu_init()
2322 tmp |= ENABLE_TC128; in r600_gpu_init()
2323 WREG32(ARB_POP, tmp); in r600_gpu_init()
2669 u32 tmp; in r600_cp_resume() local
2681 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in r600_cp_resume()
2683 tmp |= BUF_SWAP_32BIT; in r600_cp_resume()
2685 WREG32(CP_RB_CNTL, tmp); in r600_cp_resume()
2692 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); in r600_cp_resume()
2706 tmp |= RB_NO_UPDATE; in r600_cp_resume()
2711 WREG32(CP_RB_CNTL, tmp); in r600_cp_resume()
2776 uint32_t tmp = 0; in r600_ring_test() local
2797 tmp = RREG32(scratch); in r600_ring_test()
2798 if (tmp == 0xDEADBEEF) in r600_ring_test()
2806 ring->idx, scratch, tmp); in r600_ring_test()
2923 u32 size_in_bytes, cur_size_in_bytes, tmp; in r600_copy_cpdma() local
2949 tmp = upper_32_bits(src_offset) & 0xff; in r600_copy_cpdma()
2951 tmp |= PACKET3_CP_DMA_CP_SYNC; in r600_copy_cpdma()
2954 radeon_ring_write(ring, tmp); in r600_copy_cpdma()
3313 uint32_t tmp = 0; in r600_ib_test() local
3343 tmp = RREG32(scratch); in r600_ib_test()
3344 if (tmp == 0xDEADBEEF) in r600_ib_test()
3352 scratch, tmp); in r600_ib_test()
3527 u32 tmp; in r600_disable_interrupt_state() local
3530 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; in r600_disable_interrupt_state()
3531 WREG32(DMA_CNTL, tmp); in r600_disable_interrupt_state()
3539 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3540 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3541 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3542 WREG32(DC_HPD2_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3543 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3544 WREG32(DC_HPD3_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3545 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3546 WREG32(DC_HPD4_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3548 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3549 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3550 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3551 WREG32(DC_HPD6_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3552 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3553 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); in r600_disable_interrupt_state()
3554 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3555 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); in r600_disable_interrupt_state()
3557 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3558 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); in r600_disable_interrupt_state()
3559 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3560 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); in r600_disable_interrupt_state()
3565 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_disable_interrupt_state()
3566 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3567 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_disable_interrupt_state()
3568 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3569 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY; in r600_disable_interrupt_state()
3570 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3571 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3572 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); in r600_disable_interrupt_state()
3573 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK; in r600_disable_interrupt_state()
3574 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); in r600_disable_interrupt_state()
3821 u32 tmp; in r600_irq_ack() local
3858 tmp = RREG32(DC_HPD1_INT_CONTROL); in r600_irq_ack()
3859 tmp |= DC_HPDx_INT_ACK; in r600_irq_ack()
3860 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_irq_ack()
3862 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL); in r600_irq_ack()
3863 tmp |= DC_HPDx_INT_ACK; in r600_irq_ack()
3864 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); in r600_irq_ack()
3869 tmp = RREG32(DC_HPD2_INT_CONTROL); in r600_irq_ack()
3870 tmp |= DC_HPDx_INT_ACK; in r600_irq_ack()
3871 WREG32(DC_HPD2_INT_CONTROL, tmp); in r600_irq_ack()
3873 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL); in r600_irq_ack()
3874 tmp |= DC_HPDx_INT_ACK; in r600_irq_ack()
3875 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); in r600_irq_ack()
3880 tmp = RREG32(DC_HPD3_INT_CONTROL); in r600_irq_ack()
3881 tmp |= DC_HPDx_INT_ACK; in r600_irq_ack()
3882 WREG32(DC_HPD3_INT_CONTROL, tmp); in r600_irq_ack()
3884 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL); in r600_irq_ack()
3885 tmp |= DC_HPDx_INT_ACK; in r600_irq_ack()
3886 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); in r600_irq_ack()
3890 tmp = RREG32(DC_HPD4_INT_CONTROL); in r600_irq_ack()
3891 tmp |= DC_HPDx_INT_ACK; in r600_irq_ack()
3892 WREG32(DC_HPD4_INT_CONTROL, tmp); in r600_irq_ack()
3896 tmp = RREG32(DC_HPD5_INT_CONTROL); in r600_irq_ack()
3897 tmp |= DC_HPDx_INT_ACK; in r600_irq_ack()
3898 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_irq_ack()
3901 tmp = RREG32(DC_HPD5_INT_CONTROL); in r600_irq_ack()
3902 tmp |= DC_HPDx_INT_ACK; in r600_irq_ack()
3903 WREG32(DC_HPD6_INT_CONTROL, tmp); in r600_irq_ack()
3906 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0); in r600_irq_ack()
3907 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; in r600_irq_ack()
3908 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); in r600_irq_ack()
3911 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1); in r600_irq_ack()
3912 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK; in r600_irq_ack()
3913 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); in r600_irq_ack()
3917 tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL); in r600_irq_ack()
3918 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; in r600_irq_ack()
3919 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); in r600_irq_ack()
3923 tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL); in r600_irq_ack()
3924 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; in r600_irq_ack()
3925 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); in r600_irq_ack()
3927 tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL); in r600_irq_ack()
3928 tmp |= HDMI0_AZ_FORMAT_WTRIG_ACK; in r600_irq_ack()
3929 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); in r600_irq_ack()
3946 u32 wptr, tmp; in r600_get_ih_wptr() local
3962 tmp = RREG32(IH_RB_CNTL); in r600_get_ih_wptr()
3963 tmp |= IH_WPTR_OVERFLOW_CLEAR; in r600_get_ih_wptr()
3964 WREG32(IH_RB_CNTL, tmp); in r600_get_ih_wptr()
4297 u32 tmp; in r600_mmio_hdp_flush() local
4300 tmp = readl((void __iomem *)ptr); in r600_mmio_hdp_flush()
4397 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; in r600_pcie_gen2_enable() local
4473 tmp = RREG32(0x541c); in r600_pcie_gen2_enable()
4474 WREG32(0x541c, tmp | 0x8); in r600_pcie_gen2_enable()