130 		*val = RREG32(reg);  in r600_get_allowed_info_register()
299 	u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>  in rv6xx_get_temp()
744 	if (RREG32(GRBM_STATUS) & GUI_ACTIVE)  in r600_gui_idle()
758 			if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)  in r600_hpd_sense()
762 			if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)  in r600_hpd_sense()
766 			if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)  in r600_hpd_sense()
770 			if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)  in r600_hpd_sense()
775 			if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)  in r600_hpd_sense()
779 			if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)  in r600_hpd_sense()
788 			if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)  in r600_hpd_sense()
792 			if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)  in r600_hpd_sense()
796 			if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)  in r600_hpd_sense()
815 			tmp = RREG32(DC_HPD1_INT_CONTROL);  in r600_hpd_set_polarity()
823 			tmp = RREG32(DC_HPD2_INT_CONTROL);  in r600_hpd_set_polarity()
831 			tmp = RREG32(DC_HPD3_INT_CONTROL);  in r600_hpd_set_polarity()
839 			tmp = RREG32(DC_HPD4_INT_CONTROL);  in r600_hpd_set_polarity()
847 			tmp = RREG32(DC_HPD5_INT_CONTROL);  in r600_hpd_set_polarity()
856 			tmp = RREG32(DC_HPD6_INT_CONTROL);  in r600_hpd_set_polarity()
869 			tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);  in r600_hpd_set_polarity()
877 			tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);  in r600_hpd_set_polarity()
885 			tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);  in r600_hpd_set_polarity()
1045 		tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);  in r600_pcie_gart_tlb_flush()
1215 		tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;  in r600_mc_wait_for_idle()
1230 	r = RREG32(R_0028FC_MC_DATA);  in rs780_mc_rreg()
1370 			base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;  in r600_vram_gtt_location()
1388 	tmp = RREG32(RAMCFG);  in r600_mc_init()
1396 	tmp = RREG32(CHMAP);  in r600_mc_init()
1417 	rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);  in r600_mc_init()
1418 	rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);  in r600_mc_init()
1502 	u32 tmp = RREG32(R600_BIOS_3_SCRATCH);  in r600_set_bios_scratch_engine_hung()
1515 		 RREG32(R_008010_GRBM_STATUS));  in r600_print_gpu_status_regs()
1517 		 RREG32(R_008014_GRBM_STATUS2));  in r600_print_gpu_status_regs()
1519 		 RREG32(R_000E50_SRBM_STATUS));  in r600_print_gpu_status_regs()
1521 		 RREG32(CP_STALLED_STAT1));  in r600_print_gpu_status_regs()
1523 		 RREG32(CP_STALLED_STAT2));  in r600_print_gpu_status_regs()
1525 		 RREG32(CP_BUSY_STAT));  in r600_print_gpu_status_regs()
1527 		 RREG32(CP_STAT));  in r600_print_gpu_status_regs()
1529 		RREG32(DMA_STATUS_REG));  in r600_print_gpu_status_regs()
1539 		if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) {  in r600_is_display_hung()
1540 			crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);  in r600_is_display_hung()
1548 				tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]);  in r600_is_display_hung()
1567 	tmp = RREG32(R_008010_GRBM_STATUS);  in r600_gpu_check_soft_reset()
1592 	tmp = RREG32(DMA_STATUS_REG);  in r600_gpu_check_soft_reset()
1597 	tmp = RREG32(R_000E50_SRBM_STATUS);  in r600_gpu_check_soft_reset()
1654 		tmp = RREG32(DMA_RB_CNTL);  in r600_gpu_soft_reset()
1730 		tmp = RREG32(R_008020_GRBM_SOFT_RESET);  in r600_gpu_soft_reset()
1734 		tmp = RREG32(R_008020_GRBM_SOFT_RESET);  in r600_gpu_soft_reset()
1740 		tmp = RREG32(R_008020_GRBM_SOFT_RESET);  in r600_gpu_soft_reset()
1744 		tmp = RREG32(SRBM_SOFT_RESET);  in r600_gpu_soft_reset()
1748 		tmp = RREG32(SRBM_SOFT_RESET);  in r600_gpu_soft_reset()
1754 		tmp = RREG32(SRBM_SOFT_RESET);  in r600_gpu_soft_reset()
1785 	tmp = RREG32(DMA_RB_CNTL);  in r600_gpu_pci_config_reset()
1803 	tmp = RREG32(BUS_CNTL);  in r600_gpu_pci_config_reset()
1807 	tmp = RREG32(BIF_SCRATCH0);  in r600_gpu_pci_config_reset()
1821 		if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)  in r600_gpu_pci_config_reset()
2028 	ramcfg = RREG32(RAMCFG);  in r600_gpu_init()
2060 	cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0x00ffff00;  in r600_gpu_init()
2065 	disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R6XX_MAX_BACKENDS_MASK;  in r600_gpu_init()
2100 	tmp = RREG32(SX_DEBUG_1);  in r600_gpu_init()
2125 	tmp = RREG32(SQ_MS_FIFO_SIZES);  in r600_gpu_init()
2144 	sq_config = RREG32(SQ_CONFIG);  in r600_gpu_init()
2318 	tmp = RREG32(HDP_HOST_PATH_CNTL);  in r600_gpu_init()
2321 	tmp = RREG32(ARB_POP);  in r600_gpu_init()
2343 	(void)RREG32(PCIE_PORT_INDEX);  in r600_pciep_rreg()
2344 	r = RREG32(PCIE_PORT_DATA);  in r600_pciep_rreg()
2355 	(void)RREG32(PCIE_PORT_INDEX);  in r600_pciep_wreg()
2357 	(void)RREG32(PCIE_PORT_DATA);  in r600_pciep_wreg()
2572 		rptr = RREG32(R600_CP_RB_RPTR);  in r600_gfx_get_rptr()
2582 	wptr = RREG32(R600_CP_RB_WPTR);  in r600_gfx_get_wptr()
2591 	(void)RREG32(R600_CP_RB_WPTR);  in r600_gfx_set_wptr()
2612 	RREG32(GRBM_SOFT_RESET);  in r600_cp_load_microcode()
2675 	RREG32(GRBM_SOFT_RESET);  in r600_cp_resume()
2797 		tmp = RREG32(scratch);  in r600_ring_test()
3097 	temp = RREG32(CONFIG_CNTL);  in r600_vga_set_state()
3343 		tmp = RREG32(scratch);  in r600_ib_test()
3444 		RREG32(SRBM_SOFT_RESET);  in r600_rlc_stop()
3447 		RREG32(SRBM_SOFT_RESET);  in r600_rlc_stop()
3499 	u32 ih_cntl = RREG32(IH_CNTL);  in r600_enable_interrupts()
3500 	u32 ih_rb_cntl = RREG32(IH_RB_CNTL);  in r600_enable_interrupts()
3511 	u32 ih_rb_cntl = RREG32(IH_RB_CNTL);  in r600_disable_interrupts()
3512 	u32 ih_cntl = RREG32(IH_CNTL);  in r600_disable_interrupts()
3530 	tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;  in r600_disable_interrupt_state()
3539 		tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;  in r600_disable_interrupt_state()
3541 		tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;  in r600_disable_interrupt_state()
3543 		tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;  in r600_disable_interrupt_state()
3545 		tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;  in r600_disable_interrupt_state()
3548 			tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;  in r600_disable_interrupt_state()
3550 			tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;  in r600_disable_interrupt_state()
3552 			tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;  in r600_disable_interrupt_state()
3554 			tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;  in r600_disable_interrupt_state()
3557 			tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;  in r600_disable_interrupt_state()
3559 			tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;  in r600_disable_interrupt_state()
3565 		tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;  in r600_disable_interrupt_state()
3567 		tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;  in r600_disable_interrupt_state()
3569 		tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;  in r600_disable_interrupt_state()
3571 		tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;  in r600_disable_interrupt_state()
3573 		tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;  in r600_disable_interrupt_state()
3605 	interrupt_cntl = RREG32(INTERRUPT_CNTL);  in r600_irq_init()
3691 		hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;  in r600_irq_set()
3692 		hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;  in r600_irq_set()
3693 		hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;  in r600_irq_set()
3694 		hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;  in r600_irq_set()
3696 			hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;  in r600_irq_set()
3697 			hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;  in r600_irq_set()
3698 			hdmi0 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0) & ~AFMT_AZ_FORMAT_WTRIG_MASK;  in r600_irq_set()
3699 			hdmi1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1) & ~AFMT_AZ_FORMAT_WTRIG_MASK;  in r600_irq_set()
3701 			hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;  in r600_irq_set()
3702 			hdmi1 = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;  in r600_irq_set()
3705 		hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;  in r600_irq_set()
3706 		hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;  in r600_irq_set()
3707 		hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;  in r600_irq_set()
3708 		hdmi0 = RREG32(HDMI0_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;  in r600_irq_set()
3709 		hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;  in r600_irq_set()
3712 	dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;  in r600_irq_set()
3715 		thermal_int = RREG32(CG_THERMAL_INT) &  in r600_irq_set()
3718 		thermal_int = RREG32(RV770_CG_THERMAL_INT) &  in r600_irq_set()
3814 	RREG32(R_000E50_SRBM_STATUS);  in r600_irq_set()
3824 		rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);  in r600_irq_ack()
3825 		rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);  in r600_irq_ack()
3826 		rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);  in r600_irq_ack()
3828 			rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0);  in r600_irq_ack()
3829 			rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1);  in r600_irq_ack()
3831 			rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);  in r600_irq_ack()
3832 			rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS);  in r600_irq_ack()
3835 		rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);  in r600_irq_ack()
3836 		rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);  in r600_irq_ack()
3838 		rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS);  in r600_irq_ack()
3839 		rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS);  in r600_irq_ack()
3841 	rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);  in r600_irq_ack()
3842 	rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);  in r600_irq_ack()
3858 			tmp = RREG32(DC_HPD1_INT_CONTROL);  in r600_irq_ack()
3862 			tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);  in r600_irq_ack()
3869 			tmp = RREG32(DC_HPD2_INT_CONTROL);  in r600_irq_ack()
3873 			tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);  in r600_irq_ack()
3880 			tmp = RREG32(DC_HPD3_INT_CONTROL);  in r600_irq_ack()
3884 			tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);  in r600_irq_ack()
3890 		tmp = RREG32(DC_HPD4_INT_CONTROL);  in r600_irq_ack()
3896 			tmp = RREG32(DC_HPD5_INT_CONTROL);  in r600_irq_ack()
3901 			tmp = RREG32(DC_HPD5_INT_CONTROL);  in r600_irq_ack()
3906 			tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0);  in r600_irq_ack()
3911 			tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1);  in r600_irq_ack()
3917 			tmp = RREG32(HDMI0_AUDIO_PACKET_CONTROL);  in r600_irq_ack()
3923 				tmp = RREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL);  in r600_irq_ack()
3927 				tmp = RREG32(HDMI1_AUDIO_PACKET_CONTROL);  in r600_irq_ack()
3951 		wptr = RREG32(IH_RB_WPTR);  in r600_get_ih_wptr()
3962 		tmp = RREG32(IH_RB_CNTL);  in r600_get_ih_wptr()
4014 		RREG32(IH_RB_WPTR);  in r600_irq_process()
4459 			link_cntl2 = RREG32(0x4088);  in r600_pcie_gen2_enable()
4473 		tmp = RREG32(0x541c);  in r600_pcie_gen2_enable()
4523 	clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |  in r600_get_gpu_clock_counter()
4524 	        ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);  in r600_get_gpu_clock_counter()