Lines Matching refs:WREG32
293 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce3_program_fmt()
820 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_hpd_set_polarity()
828 WREG32(DC_HPD2_INT_CONTROL, tmp); in r600_hpd_set_polarity()
836 WREG32(DC_HPD3_INT_CONTROL, tmp); in r600_hpd_set_polarity()
844 WREG32(DC_HPD4_INT_CONTROL, tmp); in r600_hpd_set_polarity()
852 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_hpd_set_polarity()
861 WREG32(DC_HPD6_INT_CONTROL, tmp); in r600_hpd_set_polarity()
874 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); in r600_hpd_set_polarity()
882 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); in r600_hpd_set_polarity()
890 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); in r600_hpd_set_polarity()
922 WREG32(DC_HPD1_CONTROL, tmp); in r600_hpd_init()
925 WREG32(DC_HPD2_CONTROL, tmp); in r600_hpd_init()
928 WREG32(DC_HPD3_CONTROL, tmp); in r600_hpd_init()
931 WREG32(DC_HPD4_CONTROL, tmp); in r600_hpd_init()
935 WREG32(DC_HPD5_CONTROL, tmp); in r600_hpd_init()
938 WREG32(DC_HPD6_CONTROL, tmp); in r600_hpd_init()
946 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN); in r600_hpd_init()
949 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN); in r600_hpd_init()
952 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN); in r600_hpd_init()
975 WREG32(DC_HPD1_CONTROL, 0); in r600_hpd_fini()
978 WREG32(DC_HPD2_CONTROL, 0); in r600_hpd_fini()
981 WREG32(DC_HPD3_CONTROL, 0); in r600_hpd_fini()
984 WREG32(DC_HPD4_CONTROL, 0); in r600_hpd_fini()
988 WREG32(DC_HPD5_CONTROL, 0); in r600_hpd_fini()
991 WREG32(DC_HPD6_CONTROL, 0); in r600_hpd_fini()
999 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0); in r600_hpd_fini()
1002 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0); in r600_hpd_fini()
1005 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0); in r600_hpd_fini()
1035 WREG32(HDP_DEBUG1, 0); in r600_pcie_gart_tlb_flush()
1038 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); in r600_pcie_gart_tlb_flush()
1040 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); in r600_pcie_gart_tlb_flush()
1041 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); in r600_pcie_gart_tlb_flush()
1042 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1)); in r600_pcie_gart_tlb_flush()
1088 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in r600_pcie_gart_enable()
1091 WREG32(VM_L2_CNTL2, 0); in r600_pcie_gart_enable()
1092 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); in r600_pcie_gart_enable()
1098 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); in r600_pcie_gart_enable()
1099 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); in r600_pcie_gart_enable()
1100 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); in r600_pcie_gart_enable()
1101 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); in r600_pcie_gart_enable()
1102 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); in r600_pcie_gart_enable()
1103 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); in r600_pcie_gart_enable()
1104 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); in r600_pcie_gart_enable()
1105 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); in r600_pcie_gart_enable()
1106 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); in r600_pcie_gart_enable()
1107 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); in r600_pcie_gart_enable()
1108 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); in r600_pcie_gart_enable()
1109 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); in r600_pcie_gart_enable()
1110 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); in r600_pcie_gart_enable()
1111 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); in r600_pcie_gart_enable()
1112 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); in r600_pcie_gart_enable()
1113 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); in r600_pcie_gart_enable()
1114 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in r600_pcie_gart_enable()
1115 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in r600_pcie_gart_enable()
1116 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in r600_pcie_gart_enable()
1117 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in r600_pcie_gart_enable()
1119 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, in r600_pcie_gart_enable()
1122 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in r600_pcie_gart_enable()
1139 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in r600_pcie_gart_disable()
1142 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | in r600_pcie_gart_disable()
1144 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); in r600_pcie_gart_disable()
1148 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); in r600_pcie_gart_disable()
1149 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); in r600_pcie_gart_disable()
1150 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); in r600_pcie_gart_disable()
1151 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); in r600_pcie_gart_disable()
1152 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); in r600_pcie_gart_disable()
1153 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); in r600_pcie_gart_disable()
1154 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); in r600_pcie_gart_disable()
1155 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); in r600_pcie_gart_disable()
1156 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp); in r600_pcie_gart_disable()
1157 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp); in r600_pcie_gart_disable()
1158 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); in r600_pcie_gart_disable()
1159 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); in r600_pcie_gart_disable()
1160 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp); in r600_pcie_gart_disable()
1161 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); in r600_pcie_gart_disable()
1162 WREG32(MC_VM_L1_TLB_MCB_RD_UVD_CNTL, tmp); in r600_pcie_gart_disable()
1163 WREG32(MC_VM_L1_TLB_MCB_WR_UVD_CNTL, tmp); in r600_pcie_gart_disable()
1180 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in r600_agp_enable()
1183 WREG32(VM_L2_CNTL2, 0); in r600_agp_enable()
1184 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1)); in r600_agp_enable()
1190 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp); in r600_agp_enable()
1191 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp); in r600_agp_enable()
1192 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING); in r600_agp_enable()
1193 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp); in r600_agp_enable()
1194 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp); in r600_agp_enable()
1195 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp); in r600_agp_enable()
1196 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp); in r600_agp_enable()
1197 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp); in r600_agp_enable()
1198 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp); in r600_agp_enable()
1199 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp); in r600_agp_enable()
1200 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp); in r600_agp_enable()
1201 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp); in r600_agp_enable()
1202 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); in r600_agp_enable()
1203 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE); in r600_agp_enable()
1205 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); in r600_agp_enable()
1229 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg)); in rs780_mc_rreg()
1231 WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR); in rs780_mc_rreg()
1241 WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) | in rs780_mc_wreg()
1243 WREG32(R_0028FC_MC_DATA, v); in rs780_mc_wreg()
1244 WREG32(R_0028F8_MC_INDEX, 0x7F); in rs780_mc_wreg()
1256 WREG32((0x2c14 + j), 0x00000000); in r600_mc_program()
1257 WREG32((0x2c18 + j), 0x00000000); in r600_mc_program()
1258 WREG32((0x2c1c + j), 0x00000000); in r600_mc_program()
1259 WREG32((0x2c20 + j), 0x00000000); in r600_mc_program()
1260 WREG32((0x2c24 + j), 0x00000000); in r600_mc_program()
1262 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); in r600_mc_program()
1269 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); in r600_mc_program()
1274 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in r600_mc_program()
1276 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in r600_mc_program()
1280 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in r600_mc_program()
1282 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in r600_mc_program()
1286 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); in r600_mc_program()
1287 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); in r600_mc_program()
1289 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in r600_mc_program()
1292 WREG32(MC_VM_FB_LOCATION, tmp); in r600_mc_program()
1293 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in r600_mc_program()
1294 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); in r600_mc_program()
1295 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); in r600_mc_program()
1297 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); in r600_mc_program()
1298 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); in r600_mc_program()
1299 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); in r600_mc_program()
1301 WREG32(MC_VM_AGP_BASE, 0); in r600_mc_program()
1302 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); in r600_mc_program()
1303 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); in r600_mc_program()
1509 WREG32(R600_BIOS_3_SCRATCH, tmp); in r600_set_bios_scratch_engine_hung()
1645 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); in r600_gpu_soft_reset()
1647 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); in r600_gpu_soft_reset()
1650 WREG32(RLC_CNTL, 0); in r600_gpu_soft_reset()
1656 WREG32(DMA_RB_CNTL, tmp); in r600_gpu_soft_reset()
1733 WREG32(R_008020_GRBM_SOFT_RESET, tmp); in r600_gpu_soft_reset()
1739 WREG32(R_008020_GRBM_SOFT_RESET, tmp); in r600_gpu_soft_reset()
1747 WREG32(SRBM_SOFT_RESET, tmp); in r600_gpu_soft_reset()
1753 WREG32(SRBM_SOFT_RESET, tmp); in r600_gpu_soft_reset()
1777 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1) | S_0086D8_CP_PFP_HALT(1)); in r600_gpu_pci_config_reset()
1779 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); in r600_gpu_pci_config_reset()
1782 WREG32(RLC_CNTL, 0); in r600_gpu_pci_config_reset()
1787 WREG32(DMA_RB_CNTL, tmp); in r600_gpu_pci_config_reset()
1805 WREG32(BUS_CNTL, tmp); in r600_gpu_pci_config_reset()
1815 WREG32(SRBM_SOFT_RESET, tmp); in r600_gpu_pci_config_reset()
1817 WREG32(SRBM_SOFT_RESET, 0); in r600_gpu_pci_config_reset()
2017 WREG32((0x2c14 + j), 0x00000000); in r600_gpu_init()
2018 WREG32((0x2c18 + j), 0x00000000); in r600_gpu_init()
2019 WREG32((0x2c1c + j), 0x00000000); in r600_gpu_init()
2020 WREG32((0x2c20 + j), 0x00000000); in r600_gpu_init()
2021 WREG32((0x2c24 + j), 0x00000000); in r600_gpu_init()
2024 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); in r600_gpu_init()
2081 WREG32(GB_TILING_CONFIG, tiling_config); in r600_gpu_init()
2082 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff); in r600_gpu_init()
2083 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff); in r600_gpu_init()
2084 WREG32(DMA_TILING_CONFIG, tiling_config & 0xffff); in r600_gpu_init()
2087 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK); in r600_gpu_init()
2088 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK); in r600_gpu_init()
2091 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b))); in r600_gpu_init()
2092 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40))); in r600_gpu_init()
2094 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT | in r600_gpu_init()
2098 WREG32(ARB_GDEC_RD_CNTL, 0x00000021); in r600_gpu_init()
2104 WREG32(SX_DEBUG_1, tmp); in r600_gpu_init()
2112 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE); in r600_gpu_init()
2114 WREG32(DB_DEBUG, 0); in r600_gpu_init()
2116 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) | in r600_gpu_init()
2119 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); in r600_gpu_init()
2120 WREG32(VGT_NUM_INSTANCES, 0); in r600_gpu_init()
2122 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); in r600_gpu_init()
2123 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0)); in r600_gpu_init()
2139 WREG32(SQ_MS_FIFO_SIZES, tmp); in r600_gpu_init()
2221 WREG32(SQ_CONFIG, sq_config); in r600_gpu_init()
2222 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1); in r600_gpu_init()
2223 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2); in r600_gpu_init()
2224 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); in r600_gpu_init()
2225 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1); in r600_gpu_init()
2226 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2); in r600_gpu_init()
2232 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY)); in r600_gpu_init()
2234 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC)); in r600_gpu_init()
2238 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) | in r600_gpu_init()
2240 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) | in r600_gpu_init()
2244 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) | in r600_gpu_init()
2248 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) | in r600_gpu_init()
2253 WREG32(VGT_STRMOUT_EN, 0); in r600_gpu_init()
2271 WREG32(VGT_ES_PER_GS, 128); in r600_gpu_init()
2272 WREG32(VGT_GS_PER_ES, tmp); in r600_gpu_init()
2273 WREG32(VGT_GS_PER_VS, 2); in r600_gpu_init()
2274 WREG32(VGT_GS_VERTEX_REUSE, 16); in r600_gpu_init()
2277 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); in r600_gpu_init()
2278 WREG32(VGT_STRMOUT_EN, 0); in r600_gpu_init()
2279 WREG32(SX_MISC, 0); in r600_gpu_init()
2280 WREG32(PA_SC_MODE_CNTL, 0); in r600_gpu_init()
2281 WREG32(PA_SC_AA_CONFIG, 0); in r600_gpu_init()
2282 WREG32(PA_SC_LINE_STIPPLE, 0); in r600_gpu_init()
2283 WREG32(SPI_INPUT_Z, 0); in r600_gpu_init()
2284 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); in r600_gpu_init()
2285 WREG32(CB_COLOR7_FRAG, 0); in r600_gpu_init()
2288 WREG32(CB_COLOR0_BASE, 0); in r600_gpu_init()
2289 WREG32(CB_COLOR1_BASE, 0); in r600_gpu_init()
2290 WREG32(CB_COLOR2_BASE, 0); in r600_gpu_init()
2291 WREG32(CB_COLOR3_BASE, 0); in r600_gpu_init()
2292 WREG32(CB_COLOR4_BASE, 0); in r600_gpu_init()
2293 WREG32(CB_COLOR5_BASE, 0); in r600_gpu_init()
2294 WREG32(CB_COLOR6_BASE, 0); in r600_gpu_init()
2295 WREG32(CB_COLOR7_BASE, 0); in r600_gpu_init()
2296 WREG32(CB_COLOR7_FRAG, 0); in r600_gpu_init()
2316 WREG32(TC_CNTL, tmp); in r600_gpu_init()
2319 WREG32(HDP_HOST_PATH_CNTL, tmp); in r600_gpu_init()
2323 WREG32(ARB_POP, tmp); in r600_gpu_init()
2325 WREG32(PA_SC_MULTI_CHIP_CNTL, 0); in r600_gpu_init()
2326 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | in r600_gpu_init()
2328 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095)); in r600_gpu_init()
2329 WREG32(VC_ENHANCE, 0); in r600_gpu_init()
2342 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); in r600_pciep_rreg()
2354 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); in r600_pciep_wreg()
2356 WREG32(PCIE_PORT_DATA, (v)); in r600_pciep_wreg()
2368 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1)); in r600_cp_stop()
2369 WREG32(SCRATCH_UMSK, 0); in r600_cp_stop()
2590 WREG32(R600_CP_RB_WPTR, ring->wptr); in r600_gfx_set_wptr()
2604 WREG32(CP_RB_CNTL, in r600_cp_load_microcode()
2611 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); in r600_cp_load_microcode()
2614 WREG32(GRBM_SOFT_RESET, 0); in r600_cp_load_microcode()
2616 WREG32(CP_ME_RAM_WADDR, 0); in r600_cp_load_microcode()
2619 WREG32(CP_ME_RAM_WADDR, 0); in r600_cp_load_microcode()
2621 WREG32(CP_ME_RAM_DATA, in r600_cp_load_microcode()
2625 WREG32(CP_PFP_UCODE_ADDR, 0); in r600_cp_load_microcode()
2627 WREG32(CP_PFP_UCODE_DATA, in r600_cp_load_microcode()
2630 WREG32(CP_PFP_UCODE_ADDR, 0); in r600_cp_load_microcode()
2631 WREG32(CP_ME_RAM_WADDR, 0); in r600_cp_load_microcode()
2632 WREG32(CP_ME_RAM_RADDR, 0); in r600_cp_load_microcode()
2662 WREG32(R_0086D8_CP_ME_CNTL, cp_me); in r600_cp_start()
2674 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); in r600_cp_resume()
2677 WREG32(GRBM_SOFT_RESET, 0); in r600_cp_resume()
2685 WREG32(CP_RB_CNTL, tmp); in r600_cp_resume()
2686 WREG32(CP_SEM_WAIT_TIMER, 0x0); in r600_cp_resume()
2689 WREG32(CP_RB_WPTR_DELAY, 0); in r600_cp_resume()
2692 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); in r600_cp_resume()
2693 WREG32(CP_RB_RPTR_WR, 0); in r600_cp_resume()
2695 WREG32(CP_RB_WPTR, ring->wptr); in r600_cp_resume()
2698 WREG32(CP_RB_RPTR_ADDR, in r600_cp_resume()
2700 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in r600_cp_resume()
2701 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in r600_cp_resume()
2704 WREG32(SCRATCH_UMSK, 0xff); in r600_cp_resume()
2707 WREG32(SCRATCH_UMSK, 0); in r600_cp_resume()
2711 WREG32(CP_RB_CNTL, tmp); in r600_cp_resume()
2713 WREG32(CP_RB_BASE, ring->gpu_addr >> 8); in r600_cp_resume()
2714 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); in r600_cp_resume()
2785 WREG32(scratch, 0xCAFEDEAD); in r600_ring_test()
3104 WREG32(CONFIG_CNTL, temp); in r600_vga_set_state()
3322 WREG32(scratch, 0xCAFEDEAD); in r600_ib_test()
3443 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); in r600_rlc_stop()
3446 WREG32(SRBM_SOFT_RESET, 0); in r600_rlc_stop()
3450 WREG32(RLC_CNTL, 0); in r600_rlc_stop()
3455 WREG32(RLC_CNTL, RLC_ENABLE); in r600_rlc_start()
3468 WREG32(RLC_HB_CNTL, 0); in r600_rlc_resume()
3470 WREG32(RLC_HB_BASE, 0); in r600_rlc_resume()
3471 WREG32(RLC_HB_RPTR, 0); in r600_rlc_resume()
3472 WREG32(RLC_HB_WPTR, 0); in r600_rlc_resume()
3473 WREG32(RLC_HB_WPTR_LSB_ADDR, 0); in r600_rlc_resume()
3474 WREG32(RLC_HB_WPTR_MSB_ADDR, 0); in r600_rlc_resume()
3475 WREG32(RLC_MC_CNTL, 0); in r600_rlc_resume()
3476 WREG32(RLC_UCODE_CNTL, 0); in r600_rlc_resume()
3481 WREG32(RLC_UCODE_ADDR, i); in r600_rlc_resume()
3482 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); in r600_rlc_resume()
3486 WREG32(RLC_UCODE_ADDR, i); in r600_rlc_resume()
3487 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); in r600_rlc_resume()
3490 WREG32(RLC_UCODE_ADDR, 0); in r600_rlc_resume()
3504 WREG32(IH_CNTL, ih_cntl); in r600_enable_interrupts()
3505 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_enable_interrupts()
3516 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_disable_interrupts()
3517 WREG32(IH_CNTL, ih_cntl); in r600_disable_interrupts()
3519 WREG32(IH_RB_RPTR, 0); in r600_disable_interrupts()
3520 WREG32(IH_RB_WPTR, 0); in r600_disable_interrupts()
3529 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE); in r600_disable_interrupt_state()
3531 WREG32(DMA_CNTL, tmp); in r600_disable_interrupt_state()
3532 WREG32(GRBM_INT_CNTL, 0); in r600_disable_interrupt_state()
3533 WREG32(DxMODE_INT_MASK, 0); in r600_disable_interrupt_state()
3534 WREG32(D1GRPH_INTERRUPT_CONTROL, 0); in r600_disable_interrupt_state()
3535 WREG32(D2GRPH_INTERRUPT_CONTROL, 0); in r600_disable_interrupt_state()
3537 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0); in r600_disable_interrupt_state()
3538 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0); in r600_disable_interrupt_state()
3540 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3542 WREG32(DC_HPD2_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3544 WREG32(DC_HPD3_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3546 WREG32(DC_HPD4_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3549 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3551 WREG32(DC_HPD6_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3553 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); in r600_disable_interrupt_state()
3555 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); in r600_disable_interrupt_state()
3558 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); in r600_disable_interrupt_state()
3560 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); in r600_disable_interrupt_state()
3563 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); in r600_disable_interrupt_state()
3564 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); in r600_disable_interrupt_state()
3566 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3568 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3570 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3572 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); in r600_disable_interrupt_state()
3574 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); in r600_disable_interrupt_state()
3604 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); in r600_irq_init()
3612 WREG32(INTERRUPT_CNTL, interrupt_cntl); in r600_irq_init()
3614 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); in r600_irq_init()
3625 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); in r600_irq_init()
3626 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); in r600_irq_init()
3628 WREG32(IH_RB_CNTL, ih_rb_cntl); in r600_irq_init()
3631 WREG32(IH_RB_RPTR, 0); in r600_irq_init()
3632 WREG32(IH_RB_WPTR, 0); in r600_irq_init()
3639 WREG32(IH_CNTL, ih_cntl); in r600_irq_init()
3780 WREG32(CP_INT_CNTL, cp_int_cntl); in r600_irq_set()
3781 WREG32(DMA_CNTL, dma_cntl); in r600_irq_set()
3782 WREG32(DxMODE_INT_MASK, mode_int); in r600_irq_set()
3783 WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); in r600_irq_set()
3784 WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); in r600_irq_set()
3785 WREG32(GRBM_INT_CNTL, grbm_int_cntl); in r600_irq_set()
3787 WREG32(DC_HPD1_INT_CONTROL, hpd1); in r600_irq_set()
3788 WREG32(DC_HPD2_INT_CONTROL, hpd2); in r600_irq_set()
3789 WREG32(DC_HPD3_INT_CONTROL, hpd3); in r600_irq_set()
3790 WREG32(DC_HPD4_INT_CONTROL, hpd4); in r600_irq_set()
3792 WREG32(DC_HPD5_INT_CONTROL, hpd5); in r600_irq_set()
3793 WREG32(DC_HPD6_INT_CONTROL, hpd6); in r600_irq_set()
3794 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, hdmi0); in r600_irq_set()
3795 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, hdmi1); in r600_irq_set()
3797 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); in r600_irq_set()
3798 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, hdmi1); in r600_irq_set()
3801 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1); in r600_irq_set()
3802 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2); in r600_irq_set()
3803 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3); in r600_irq_set()
3804 WREG32(HDMI0_AUDIO_PACKET_CONTROL, hdmi0); in r600_irq_set()
3805 WREG32(HDMI1_AUDIO_PACKET_CONTROL, hdmi1); in r600_irq_set()
3808 WREG32(CG_THERMAL_INT, thermal_int); in r600_irq_set()
3810 WREG32(RV770_CG_THERMAL_INT, thermal_int); in r600_irq_set()
3845 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); in r600_irq_ack()
3847 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR); in r600_irq_ack()
3849 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); in r600_irq_ack()
3851 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK); in r600_irq_ack()
3853 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK); in r600_irq_ack()
3855 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK); in r600_irq_ack()
3860 WREG32(DC_HPD1_INT_CONTROL, tmp); in r600_irq_ack()
3864 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp); in r600_irq_ack()
3871 WREG32(DC_HPD2_INT_CONTROL, tmp); in r600_irq_ack()
3875 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp); in r600_irq_ack()
3882 WREG32(DC_HPD3_INT_CONTROL, tmp); in r600_irq_ack()
3886 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp); in r600_irq_ack()
3892 WREG32(DC_HPD4_INT_CONTROL, tmp); in r600_irq_ack()
3898 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_irq_ack()
3903 WREG32(DC_HPD6_INT_CONTROL, tmp); in r600_irq_ack()
3908 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET0, tmp); in r600_irq_ack()
3913 WREG32(AFMT_AUDIO_PACKET_CONTROL + DCE3_HDMI_OFFSET1, tmp); in r600_irq_ack()
3919 WREG32(HDMI0_AUDIO_PACKET_CONTROL, tmp); in r600_irq_ack()
3925 WREG32(DCE3_HDMI1_AUDIO_PACKET_CONTROL, tmp); in r600_irq_ack()
3929 WREG32(HDMI1_AUDIO_PACKET_CONTROL, tmp); in r600_irq_ack()
3964 WREG32(IH_RB_CNTL, tmp); in r600_get_ih_wptr()
4229 WREG32(IH_RB_RPTR, rptr); in r600_irq_process()
4299 WREG32(HDP_DEBUG1, 0); in r600_mmio_hdp_flush()
4302 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); in r600_mmio_hdp_flush()
4458 WREG32(MM_CFGREGS_CNTL, 0x8); in r600_pcie_gen2_enable()
4460 WREG32(MM_CFGREGS_CNTL, 0); in r600_pcie_gen2_enable()
4474 WREG32(0x541c, tmp | 0x8); in r600_pcie_gen2_enable()
4475 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN); in r600_pcie_gen2_enable()
4480 WREG32(MM_CFGREGS_CNTL, 0); in r600_pcie_gen2_enable()
4522 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); in r600_get_gpu_clock_counter()