3228 	rdev->ih.ring_obj = NULL;  in r600_init()
3380 	rdev->ih.ring_size = ring_size;  in r600_ih_ring_init()
3381 	rdev->ih.ptr_mask = rdev->ih.ring_size - 1;  in r600_ih_ring_init()
3382 	rdev->ih.rptr = 0;  in r600_ih_ring_init()
3390 	if (rdev->ih.ring_obj == NULL) {  in r600_ih_ring_alloc()
3391 		r = radeon_bo_create(rdev, rdev->ih.ring_size,  in r600_ih_ring_alloc()
3394 				     NULL, NULL, &rdev->ih.ring_obj);  in r600_ih_ring_alloc()
3399 		r = radeon_bo_reserve(rdev->ih.ring_obj, false);  in r600_ih_ring_alloc()
3402 		r = radeon_bo_pin(rdev->ih.ring_obj,  in r600_ih_ring_alloc()
3404 				  &rdev->ih.gpu_addr);  in r600_ih_ring_alloc()
3406 			radeon_bo_unreserve(rdev->ih.ring_obj);  in r600_ih_ring_alloc()
3410 		r = radeon_bo_kmap(rdev->ih.ring_obj,  in r600_ih_ring_alloc()
3411 				   (void **)&rdev->ih.ring);  in r600_ih_ring_alloc()
3412 		radeon_bo_unreserve(rdev->ih.ring_obj);  in r600_ih_ring_alloc()
3424 	if (rdev->ih.ring_obj) {  in r600_ih_ring_fini()
3425 		r = radeon_bo_reserve(rdev->ih.ring_obj, false);  in r600_ih_ring_fini()
3427 			radeon_bo_kunmap(rdev->ih.ring_obj);  in r600_ih_ring_fini()
3428 			radeon_bo_unpin(rdev->ih.ring_obj);  in r600_ih_ring_fini()
3429 			radeon_bo_unreserve(rdev->ih.ring_obj);  in r600_ih_ring_fini()
3431 		radeon_bo_unref(&rdev->ih.ring_obj);  in r600_ih_ring_fini()
3432 		rdev->ih.ring = NULL;  in r600_ih_ring_fini()
3433 		rdev->ih.ring_obj = NULL;  in r600_ih_ring_fini()
3506 	rdev->ih.enabled = true;  in r600_enable_interrupts()
3521 	rdev->ih.enabled = false;  in r600_disable_interrupts()
3522 	rdev->ih.rptr = 0;  in r600_disable_interrupts()
3604 	WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);  in r600_irq_init()
3614 	WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);  in r600_irq_init()
3615 	rb_bufsz = order_base_2(rdev->ih.ring_size / 4);  in r600_irq_init()
3683 	if (!rdev->ih.enabled) {  in r600_irq_set()
3960 			 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask);  in r600_get_ih_wptr()
3961 		rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;  in r600_get_ih_wptr()
3966 	return (wptr & rdev->ih.ptr_mask);  in r600_get_ih_wptr()
4009 	if (!rdev->ih.enabled || rdev->shutdown)  in r600_irq_process()
4020 	if (atomic_xchg(&rdev->ih.lock, 1))  in r600_irq_process()
4023 	rptr = rdev->ih.rptr;  in r600_irq_process()
4035 		src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;  in r600_irq_process()
4036 		src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;  in r600_irq_process()
4228 		rptr &= rdev->ih.ptr_mask;  in r600_irq_process()
4237 	rdev->ih.rptr = rptr;  in r600_irq_process()
4238 	atomic_set(&rdev->ih.lock, 0);  in r600_irq_process()