Lines Matching refs:mc
1040 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12); in r600_pcie_gart_tlb_flush()
1041 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12); in r600_pcie_gart_tlb_flush()
1114 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in r600_pcie_gart_enable()
1115 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in r600_pcie_gart_enable()
1126 (unsigned)(rdev->mc.gtt_size >> 20), in r600_pcie_gart_enable()
1272 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in r600_mc_program()
1275 rdev->mc.vram_start >> 12); in r600_mc_program()
1277 rdev->mc.gtt_end >> 12); in r600_mc_program()
1281 rdev->mc.gtt_start >> 12); in r600_mc_program()
1283 rdev->mc.vram_end >> 12); in r600_mc_program()
1286 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12); in r600_mc_program()
1287 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12); in r600_mc_program()
1290 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in r600_mc_program()
1291 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in r600_mc_program()
1293 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in r600_mc_program()
1297 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22); in r600_mc_program()
1298 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22); in r600_mc_program()
1299 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); in r600_mc_program()
1335 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) in r600_vram_gtt_location() argument
1339 if (mc->mc_vram_size > 0xE0000000) { in r600_vram_gtt_location()
1342 mc->real_vram_size = 0xE0000000; in r600_vram_gtt_location()
1343 mc->mc_vram_size = 0xE0000000; in r600_vram_gtt_location()
1346 size_bf = mc->gtt_start; in r600_vram_gtt_location()
1347 size_af = mc->mc_mask - mc->gtt_end; in r600_vram_gtt_location()
1349 if (mc->mc_vram_size > size_bf) { in r600_vram_gtt_location()
1351 mc->real_vram_size = size_bf; in r600_vram_gtt_location()
1352 mc->mc_vram_size = size_bf; in r600_vram_gtt_location()
1354 mc->vram_start = mc->gtt_start - mc->mc_vram_size; in r600_vram_gtt_location()
1356 if (mc->mc_vram_size > size_af) { in r600_vram_gtt_location()
1358 mc->real_vram_size = size_af; in r600_vram_gtt_location()
1359 mc->mc_vram_size = size_af; in r600_vram_gtt_location()
1361 mc->vram_start = mc->gtt_end + 1; in r600_vram_gtt_location()
1363 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; in r600_vram_gtt_location()
1365 mc->mc_vram_size >> 20, mc->vram_start, in r600_vram_gtt_location()
1366 mc->vram_end, mc->real_vram_size >> 20); in r600_vram_gtt_location()
1373 radeon_vram_location(rdev, &rdev->mc, base); in r600_vram_gtt_location()
1374 rdev->mc.gtt_base_align = 0; in r600_vram_gtt_location()
1375 radeon_gtt_location(rdev, mc); in r600_vram_gtt_location()
1387 rdev->mc.vram_is_ddr = true; in r600_mc_init()
1412 rdev->mc.vram_width = numchan * chansize; in r600_mc_init()
1414 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in r600_mc_init()
1415 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in r600_mc_init()
1417 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); in r600_mc_init()
1418 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); in r600_mc_init()
1419 rdev->mc.visible_vram_size = rdev->mc.aper_size; in r600_mc_init()
1420 r600_vram_gtt_location(rdev, &rdev->mc); in r600_mc_init()
1424 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); in r600_mc_init()
1433 if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL) in r600_mc_init()
1439 if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) { in r600_mc_init()
1441 (unsigned long long)rdev->mc.aper_base, k8_addr); in r600_mc_init()
1442 rdev->mc.aper_base = (resource_size_t)k8_addr; in r600_mc_init()
2367 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in r600_cp_stop()
2725 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); in r600_cp_resume()