1563 	u32 reset_mask = 0;  in r600_gpu_check_soft_reset()  local
1574 			reset_mask |= RADEON_RESET_GFX;  in r600_gpu_check_soft_reset()
1581 			reset_mask |= RADEON_RESET_GFX;  in r600_gpu_check_soft_reset()
1586 		reset_mask |= RADEON_RESET_CP;  in r600_gpu_check_soft_reset()
1589 		reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;  in r600_gpu_check_soft_reset()
1594 		reset_mask |= RADEON_RESET_DMA;  in r600_gpu_check_soft_reset()
1599 		reset_mask |= RADEON_RESET_RLC;  in r600_gpu_check_soft_reset()
1602 		reset_mask |= RADEON_RESET_IH;  in r600_gpu_check_soft_reset()
1605 		reset_mask |= RADEON_RESET_SEM;  in r600_gpu_check_soft_reset()
1608 		reset_mask |= RADEON_RESET_GRBM;  in r600_gpu_check_soft_reset()
1611 		reset_mask |= RADEON_RESET_VMC;  in r600_gpu_check_soft_reset()
1616 		reset_mask |= RADEON_RESET_MC;  in r600_gpu_check_soft_reset()
1619 		reset_mask |= RADEON_RESET_DISPLAY;  in r600_gpu_check_soft_reset()
1622 	if (reset_mask & RADEON_RESET_MC) {  in r600_gpu_check_soft_reset()
1623 		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);  in r600_gpu_check_soft_reset()
1624 		reset_mask &= ~RADEON_RESET_MC;  in r600_gpu_check_soft_reset()
1627 	return reset_mask;  in r600_gpu_check_soft_reset()
1630 static void r600_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)  in r600_gpu_soft_reset()  argument
1636 	if (reset_mask == 0)  in r600_gpu_soft_reset()
1639 	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);  in r600_gpu_soft_reset()
1652 	if (reset_mask & RADEON_RESET_DMA) {  in r600_gpu_soft_reset()
1666 	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {  in r600_gpu_soft_reset()
1695 	if (reset_mask & RADEON_RESET_CP) {  in r600_gpu_soft_reset()
1702 	if (reset_mask & RADEON_RESET_DMA) {  in r600_gpu_soft_reset()
1709 	if (reset_mask & RADEON_RESET_RLC)  in r600_gpu_soft_reset()
1712 	if (reset_mask & RADEON_RESET_SEM)  in r600_gpu_soft_reset()
1715 	if (reset_mask & RADEON_RESET_IH)  in r600_gpu_soft_reset()
1718 	if (reset_mask & RADEON_RESET_GRBM)  in r600_gpu_soft_reset()
1722 		if (reset_mask & RADEON_RESET_MC)  in r600_gpu_soft_reset()
1726 	if (reset_mask & RADEON_RESET_VMC)  in r600_gpu_soft_reset()
1829 	u32 reset_mask;  in r600_asic_reset()  local
1831 	reset_mask = r600_gpu_check_soft_reset(rdev);  in r600_asic_reset()
1833 	if (reset_mask)  in r600_asic_reset()
1837 	r600_gpu_soft_reset(rdev, reset_mask);  in r600_asic_reset()
1839 	reset_mask = r600_gpu_check_soft_reset(rdev);  in r600_asic_reset()
1842 	if (reset_mask && radeon_hard_reset)  in r600_asic_reset()
1845 	reset_mask = r600_gpu_check_soft_reset(rdev);  in r600_asic_reset()
1847 	if (!reset_mask)  in r600_asic_reset()
1864 	u32 reset_mask = r600_gpu_check_soft_reset(rdev);  in r600_gfx_is_lockup()  local
1866 	if (!(reset_mask & (RADEON_RESET_GFX |  in r600_gfx_is_lockup()