Lines Matching refs:speed_cntl
4397 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp; in r600_pcie_gen2_enable() local
4421 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in r600_pcie_gen2_enable()
4422 if (speed_cntl & LC_CURRENT_DATA_RATE) { in r600_pcie_gen2_enable()
4450 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in r600_pcie_gen2_enable()
4451 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) && in r600_pcie_gen2_enable()
4452 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) { in r600_pcie_gen2_enable()
4466 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK; in r600_pcie_gen2_enable()
4467 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT); in r600_pcie_gen2_enable()
4468 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK; in r600_pcie_gen2_enable()
4469 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE; in r600_pcie_gen2_enable()
4470 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE; in r600_pcie_gen2_enable()
4471 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in r600_pcie_gen2_enable()
4489 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in r600_pcie_gen2_enable()
4490 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN; in r600_pcie_gen2_enable()
4491 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in r600_pcie_gen2_enable()
4494 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); in r600_pcie_gen2_enable()
4495 speed_cntl |= LC_GEN2_EN_STRAP; in r600_pcie_gen2_enable()
4496 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); in r600_pcie_gen2_enable()