Lines Matching refs:wb
2569 if (rdev->wb.enabled) in r600_gfx_get_rptr()
2570 rptr = rdev->wb.wb[ring->rptr_offs/4]; in r600_gfx_get_rptr()
2699 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); in r600_cp_resume()
2700 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in r600_cp_resume()
2701 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in r600_cp_resume()
2703 if (rdev->wb.enabled) in r600_cp_resume()
2827 if (rdev->wb.use_event) { in r600_fence_ring_emit()
3290 } else if (rdev->wb.enabled) { in r600_ring_ib_execute()
3621 if (rdev->wb.enabled) in r600_irq_init()
3625 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); in r600_irq_init()
3626 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); in r600_irq_init()
3948 if (rdev->wb.enabled) in r600_get_ih_wptr()
3949 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); in r600_get_ih_wptr()