Lines Matching refs:ib
356 volatile u32 *ib = p->ib.ptr; in r600_cs_track_validate_cb() local
467 ib[track->cb_color_size_idx[i]] = tmp; in r600_cs_track_validate_cb()
526 volatile u32 *ib = p->ib.ptr; in r600_cs_track_validate_db() local
564 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF); in r600_cs_track_validate_db()
834 volatile uint32_t *ib; in r600_cs_common_vline_parse() local
836 ib = p->ib.ptr; in r600_cs_common_vline_parse()
899 ib[h_idx + 2] = PACKET2(0); in r600_cs_common_vline_parse()
900 ib[h_idx + 3] = PACKET2(0); in r600_cs_common_vline_parse()
901 ib[h_idx + 4] = PACKET2(0); in r600_cs_common_vline_parse()
902 ib[h_idx + 5] = PACKET2(0); in r600_cs_common_vline_parse()
903 ib[h_idx + 6] = PACKET2(0); in r600_cs_common_vline_parse()
904 ib[h_idx + 7] = PACKET2(0); in r600_cs_common_vline_parse()
905 ib[h_idx + 8] = PACKET2(0); in r600_cs_common_vline_parse()
909 ib[h_idx] = header; in r600_cs_common_vline_parse()
910 ib[h_idx + 4] = vline_status[crtc_id] >> 2; in r600_cs_common_vline_parse()
973 u32 m, i, tmp, *ib; in r600_cs_check_reg() local
984 ib = p->ib.ptr; in r600_cs_check_reg()
1023 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1042 ib[idx] &= C_028010_ARRAY_MODE; in r600_cs_check_reg()
1045 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); in r600_cs_check_reg()
1048 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1); in r600_cs_check_reg()
1085 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1106 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1144 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1); in r600_cs_check_reg()
1147 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1); in r600_cs_check_reg()
1206 ib[idx] = track->cb_color_base_last[tmp]; in r600_cs_check_reg()
1214 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8; in r600_cs_check_reg()
1215 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1237 ib[idx] = track->cb_color_base_last[tmp]; in r600_cs_check_reg()
1245 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8; in r600_cs_check_reg()
1246 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1282 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1283 track->cb_color_base_last[tmp] = ib[idx]; in r600_cs_check_reg()
1296 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1309 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1316 ib[idx] |= 3; in r600_cs_check_reg()
1378 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1387 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_cs_check_reg()
1631 volatile u32 *ib; in r600_packet3_check() local
1639 ib = p->ib.ptr; in r600_packet3_check()
1677 ib[idx + 0] = offset; in r600_packet3_check()
1678 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); in r600_packet3_check()
1718 ib[idx+0] = offset; in r600_packet3_check()
1719 ib[idx+1] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
1770 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0); in r600_packet3_check()
1771 ib[idx+2] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
1814 ib[idx] = offset; in r600_packet3_check()
1815 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in r600_packet3_check()
1844 ib[idx+2] = offset; in r600_packet3_check()
1845 ib[idx+3] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
1862 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
1882 ib[idx+1] = offset & 0xfffffff8; in r600_packet3_check()
1883 ib[idx+2] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
1904 ib[idx+1] = offset & 0xfffffffc; in r600_packet3_check()
1905 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in r600_packet3_check()
1968 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); in r600_packet3_check()
1970 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1); in r600_packet3_check()
1988 ib[idx+1+(i*7)+2] += base_offset; in r600_packet3_check()
1989 ib[idx+1+(i*7)+3] += mip_offset; in r600_packet3_check()
2006 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset; in r600_packet3_check()
2010 ib[idx+1+(i*8)+0] = offset64; in r600_packet3_check()
2011 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) | in r600_packet3_check()
2119 ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff); in r600_packet3_check()
2153 ib[idx+1] = offset; in r600_packet3_check()
2154 ib[idx+2] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2172 ib[idx+3] = offset; in r600_packet3_check()
2173 ib[idx+4] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2201 ib[idx+0] = offset; in r600_packet3_check()
2202 ib[idx+1] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2226 ib[idx+1] = offset; in r600_packet3_check()
2227 ib[idx+2] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2250 ib[idx+3] = offset; in r600_packet3_check()
2251 ib[idx+4] = upper_32_bits(offset) & 0xff; in r600_packet3_check()
2321 for (r = 0; r < p->ib.length_dw; r++) { in r600_cs_parse()
2322 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]); in r600_cs_parse()
2365 unsigned family, u32 *ib, int *l) in r600_cs_legacy() argument
2385 parser.ib.ptr = ib; in r600_cs_legacy()
2402 parser.ib.length_dw = ib_chunk->length_dw; in r600_cs_legacy()
2403 *l = parser.ib.length_dw; in r600_cs_legacy()
2404 if (copy_from_user(ib, ib_chunk->user_ptr, ib_chunk->length_dw * 4)) { in r600_cs_legacy()
2478 volatile u32 *ib = p->ib.ptr; in r600_dma_cs_parse() local
2506 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in r600_dma_cs_parse()
2512 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2513 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2540 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8); in r600_dma_cs_parse()
2544 ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2545 ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2550 ib[idx+5] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2551 ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2555 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8); in r600_dma_cs_parse()
2565 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2566 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2567 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2568 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2576 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2577 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2578 ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff; in r600_dma_cs_parse()
2579 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16; in r600_dma_cs_parse()
2611 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc); in r600_dma_cs_parse()
2612 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000; in r600_dma_cs_parse()
2624 for (r = 0; r < p->ib->length_dw; r++) { in r600_dma_cs_parse()
2625 printk(KERN_INFO "%05d 0x%08X\n", r, p->ib.ptr[r]); in r600_dma_cs_parse()