Lines Matching refs:post_div
38 uint32_t fb_div, ref_div, post_div, sclk; in radeon_legacy_get_engine_clock() local
53 post_div = RREG32_PLL(RADEON_SCLK_CNTL) & RADEON_SCLK_SRC_SEL_MASK; in radeon_legacy_get_engine_clock()
54 if (post_div == 2) in radeon_legacy_get_engine_clock()
56 else if (post_div == 3) in radeon_legacy_get_engine_clock()
58 else if (post_div == 4) in radeon_legacy_get_engine_clock()
68 uint32_t fb_div, ref_div, post_div, mclk; in radeon_legacy_get_memory_clock() local
83 post_div = RREG32_PLL(RADEON_MCLK_CNTL) & 0x7; in radeon_legacy_get_memory_clock()
84 if (post_div == 2) in radeon_legacy_get_memory_clock()
86 else if (post_div == 3) in radeon_legacy_get_memory_clock()
88 else if (post_div == 4) in radeon_legacy_get_memory_clock()
348 int *fb_div, int *post_div) in calc_eng_mem_clock() argument
359 *post_div = 8; in calc_eng_mem_clock()
362 *post_div = 4; in calc_eng_mem_clock()
365 *post_div = 2; in calc_eng_mem_clock()
368 *post_div = 1; in calc_eng_mem_clock()
379 req_clock /= *post_div; in calc_eng_mem_clock()
389 int fb_div, post_div; in radeon_legacy_set_engine_clock() local
393 eng_clock = calc_eng_mem_clock(rdev, eng_clock, &fb_div, &post_div); in radeon_legacy_set_engine_clock()
425 if ((eng_clock * post_div) >= 90000) in radeon_legacy_set_engine_clock()
445 switch (post_div) { in radeon_legacy_set_engine_clock()