42 		WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);  in radeon_lock_cursor()
49 		WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);  in radeon_lock_cursor()
56 		WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);  in radeon_lock_cursor()
94 		WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);  in radeon_show_cursor()
95 		WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |  in radeon_show_cursor()
99 		WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);  in radeon_show_cursor()
100 		WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |  in radeon_show_cursor()
105 			WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);  in radeon_show_cursor()
108 			WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);  in radeon_show_cursor()
186 		WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);  in radeon_cursor_move_locked()
187 		WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);  in radeon_cursor_move_locked()
188 		WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,  in radeon_cursor_move_locked()
191 		WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);  in radeon_cursor_move_locked()
192 		WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);  in radeon_cursor_move_locked()
193 		WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,  in radeon_cursor_move_locked()
199 		WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,  in radeon_cursor_move_locked()
203 		WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,  in radeon_cursor_move_locked()
208 		WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,  in radeon_cursor_move_locked()
237 		WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,  in radeon_set_cursor()
239 		WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in radeon_set_cursor()
244 				WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH,  in radeon_set_cursor()
247 				WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH,  in radeon_set_cursor()
250 		WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,  in radeon_set_cursor()
254 		WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,  in radeon_set_cursor()