Lines Matching refs:radeon_crtc
42 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in avivo_crtc_load_lut() local
47 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); in avivo_crtc_load_lut()
48 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
51 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
52 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in avivo_crtc_load_lut()
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
55 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
56 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); in avivo_crtc_load_lut()
58 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id); in avivo_crtc_load_lut()
65 (radeon_crtc->lut_r[i] << 20) | in avivo_crtc_load_lut()
66 (radeon_crtc->lut_g[i] << 10) | in avivo_crtc_load_lut()
67 (radeon_crtc->lut_b[i] << 0)); in avivo_crtc_load_lut()
71 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id, ~1); in avivo_crtc_load_lut()
76 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in dce4_crtc_load_lut() local
81 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); in dce4_crtc_load_lut()
82 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
84 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
85 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
86 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
88 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); in dce4_crtc_load_lut()
89 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); in dce4_crtc_load_lut()
90 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); in dce4_crtc_load_lut()
92 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
93 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); in dce4_crtc_load_lut()
95 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); in dce4_crtc_load_lut()
97 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, in dce4_crtc_load_lut()
98 (radeon_crtc->lut_r[i] << 20) | in dce4_crtc_load_lut()
99 (radeon_crtc->lut_g[i] << 10) | in dce4_crtc_load_lut()
100 (radeon_crtc->lut_b[i] << 0)); in dce4_crtc_load_lut()
106 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in dce5_crtc_load_lut() local
111 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); in dce5_crtc_load_lut()
113 WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
116 WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
118 WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
120 WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
124 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
126 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
127 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
128 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
130 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff); in dce5_crtc_load_lut()
131 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff); in dce5_crtc_load_lut()
132 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff); in dce5_crtc_load_lut()
134 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
135 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007); in dce5_crtc_load_lut()
137 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
139 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
140 (radeon_crtc->lut_r[i] << 20) | in dce5_crtc_load_lut()
141 (radeon_crtc->lut_g[i] << 10) | in dce5_crtc_load_lut()
142 (radeon_crtc->lut_b[i] << 0)); in dce5_crtc_load_lut()
145 WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
150 WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
153 WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
156 WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
157 (NI_OUTPUT_CSC_GRPH_MODE(radeon_crtc->output_csc) | in dce5_crtc_load_lut()
160 WREG32(0x6940 + radeon_crtc->crtc_offset, 0); in dce5_crtc_load_lut()
165 WREG32(CIK_ALPHA_CONTROL + radeon_crtc->crtc_offset, in dce5_crtc_load_lut()
172 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in legacy_crtc_load_lut() local
179 if (radeon_crtc->crtc_id == 0) in legacy_crtc_load_lut()
188 (radeon_crtc->lut_r[i] << 20) | in legacy_crtc_load_lut()
189 (radeon_crtc->lut_g[i] << 10) | in legacy_crtc_load_lut()
190 (radeon_crtc->lut_b[i] << 0)); in legacy_crtc_load_lut()
216 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_crtc_fb_gamma_set() local
218 radeon_crtc->lut_r[regno] = red >> 6; in radeon_crtc_fb_gamma_set()
219 radeon_crtc->lut_g[regno] = green >> 6; in radeon_crtc_fb_gamma_set()
220 radeon_crtc->lut_b[regno] = blue >> 6; in radeon_crtc_fb_gamma_set()
227 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_crtc_fb_gamma_get() local
229 *red = radeon_crtc->lut_r[regno] << 6; in radeon_crtc_fb_gamma_get()
230 *green = radeon_crtc->lut_g[regno] << 6; in radeon_crtc_fb_gamma_get()
231 *blue = radeon_crtc->lut_b[regno] << 6; in radeon_crtc_fb_gamma_get()
237 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_crtc_gamma_set() local
242 radeon_crtc->lut_r[i] = red[i] >> 6; in radeon_crtc_gamma_set()
243 radeon_crtc->lut_g[i] = green[i] >> 6; in radeon_crtc_gamma_set()
244 radeon_crtc->lut_b[i] = blue[i] >> 6; in radeon_crtc_gamma_set()
251 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_crtc_destroy() local
254 destroy_workqueue(radeon_crtc->flip_queue); in radeon_crtc_destroy()
255 kfree(radeon_crtc); in radeon_crtc_destroy()
288 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in radeon_crtc_handle_vblank() local
294 if (radeon_crtc == NULL) in radeon_crtc_handle_vblank()
310 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { in radeon_crtc_handle_vblank()
313 radeon_crtc->flip_status, in radeon_crtc_handle_vblank()
352 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in radeon_crtc_handle_flip() local
357 if (radeon_crtc == NULL) in radeon_crtc_handle_flip()
361 work = radeon_crtc->flip_work; in radeon_crtc_handle_flip()
362 if (radeon_crtc->flip_status != RADEON_FLIP_SUBMITTED) { in radeon_crtc_handle_flip()
365 radeon_crtc->flip_status, in radeon_crtc_handle_flip()
372 radeon_crtc->flip_status = RADEON_FLIP_NONE; in radeon_crtc_handle_flip()
373 radeon_crtc->flip_work = NULL; in radeon_crtc_handle_flip()
381 drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id); in radeon_crtc_handle_flip()
383 queue_work(radeon_crtc->flip_queue, &work->unpin_work); in radeon_crtc_handle_flip()
398 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[work->crtc_id]; in radeon_flip_work_func() local
400 struct drm_crtc *crtc = &radeon_crtc->base; in radeon_flip_work_func()
437 radeon_irq_kms_pflip_irq_get(rdev, radeon_crtc->crtc_id); in radeon_flip_work_func()
440 radeon_page_flip(rdev, radeon_crtc->crtc_id, work->base); in radeon_flip_work_func()
442 radeon_crtc->flip_status = RADEON_FLIP_SUBMITTED; in radeon_flip_work_func()
454 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_crtc_page_flip() local
473 work->crtc_id = radeon_crtc->crtc_id; in radeon_crtc_page_flip()
512 base -= radeon_crtc->legacy_display_base_addr; in radeon_crtc_page_flip()
547 r = drm_vblank_get(crtc->dev, radeon_crtc->crtc_id); in radeon_crtc_page_flip()
556 if (radeon_crtc->flip_status != RADEON_FLIP_NONE) { in radeon_crtc_page_flip()
562 radeon_crtc->flip_status = RADEON_FLIP_PENDING; in radeon_crtc_page_flip()
563 radeon_crtc->flip_work = work; in radeon_crtc_page_flip()
570 queue_work(radeon_crtc->flip_queue, &work->flip_work); in radeon_crtc_page_flip()
574 drm_vblank_put(crtc->dev, radeon_crtc->crtc_id); in radeon_crtc_page_flip()
649 struct radeon_crtc *radeon_crtc; in radeon_crtc_init() local
652 …radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connec… in radeon_crtc_init()
653 if (radeon_crtc == NULL) in radeon_crtc_init()
656 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs); in radeon_crtc_init()
658 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256); in radeon_crtc_init()
659 radeon_crtc->crtc_id = index; in radeon_crtc_init()
660 radeon_crtc->flip_queue = create_singlethread_workqueue("radeon-crtc"); in radeon_crtc_init()
661 rdev->mode_info.crtcs[index] = radeon_crtc; in radeon_crtc_init()
664 radeon_crtc->max_cursor_width = CIK_CURSOR_WIDTH; in radeon_crtc_init()
665 radeon_crtc->max_cursor_height = CIK_CURSOR_HEIGHT; in radeon_crtc_init()
667 radeon_crtc->max_cursor_width = CURSOR_WIDTH; in radeon_crtc_init()
668 radeon_crtc->max_cursor_height = CURSOR_HEIGHT; in radeon_crtc_init()
670 dev->mode_config.cursor_width = radeon_crtc->max_cursor_width; in radeon_crtc_init()
671 dev->mode_config.cursor_height = radeon_crtc->max_cursor_height; in radeon_crtc_init()
674 radeon_crtc->mode_set.crtc = &radeon_crtc->base; in radeon_crtc_init()
675 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1); in radeon_crtc_init()
676 radeon_crtc->mode_set.num_connectors = 0; in radeon_crtc_init()
680 radeon_crtc->lut_r[i] = i << 2; in radeon_crtc_init()
681 radeon_crtc->lut_g[i] = i << 2; in radeon_crtc_init()
682 radeon_crtc->lut_b[i] = i << 2; in radeon_crtc_init()
686 radeon_atombios_init_crtc(dev, radeon_crtc); in radeon_crtc_init()
688 radeon_legacy_init_crtc(dev, radeon_crtc); in radeon_crtc_init()
1677 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); in radeon_crtc_scaling_mode_fixup() local
1685 radeon_crtc->h_border = 0; in radeon_crtc_scaling_mode_fixup()
1686 radeon_crtc->v_border = 0; in radeon_crtc_scaling_mode_fixup()
1698 radeon_crtc->rmx_type = RMX_OFF; in radeon_crtc_scaling_mode_fixup()
1701 radeon_crtc->rmx_type = radeon_encoder->rmx_type; in radeon_crtc_scaling_mode_fixup()
1703 radeon_crtc->rmx_type = RMX_OFF; in radeon_crtc_scaling_mode_fixup()
1705 memcpy(&radeon_crtc->native_mode, in radeon_crtc_scaling_mode_fixup()
1709 dst_v = radeon_crtc->native_mode.vdisplay; in radeon_crtc_scaling_mode_fixup()
1711 dst_h = radeon_crtc->native_mode.hdisplay; in radeon_crtc_scaling_mode_fixup()
1721 radeon_crtc->h_border = radeon_encoder->underscan_hborder; in radeon_crtc_scaling_mode_fixup()
1723 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16; in radeon_crtc_scaling_mode_fixup()
1725 radeon_crtc->v_border = radeon_encoder->underscan_vborder; in radeon_crtc_scaling_mode_fixup()
1727 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16; in radeon_crtc_scaling_mode_fixup()
1728 radeon_crtc->rmx_type = RMX_FULL; in radeon_crtc_scaling_mode_fixup()
1730 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2); in radeon_crtc_scaling_mode_fixup()
1732 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2); in radeon_crtc_scaling_mode_fixup()
1736 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) { in radeon_crtc_scaling_mode_fixup()
1748 if (radeon_crtc->rmx_type != RMX_OFF) { in radeon_crtc_scaling_mode_fixup()
1752 radeon_crtc->vsc.full = dfixed_div(a, b); in radeon_crtc_scaling_mode_fixup()
1755 radeon_crtc->hsc.full = dfixed_div(a, b); in radeon_crtc_scaling_mode_fixup()
1757 radeon_crtc->vsc.full = dfixed_const(1); in radeon_crtc_scaling_mode_fixup()
1758 radeon_crtc->hsc.full = dfixed_const(1); in radeon_crtc_scaling_mode_fixup()