Lines Matching refs:mc
107 rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) { in radeon_ttm_placement_from_domain()
109 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; in radeon_ttm_placement_from_domain()
172 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; in radeon_ttm_placement_from_domain()
339 domain_start = bo->rdev->mc.vram_start; in radeon_bo_pin_restricted()
341 domain_start = bo->rdev->mc.gtt_start; in radeon_bo_pin_restricted()
353 (!max_offset || max_offset > bo->rdev->mc.visible_vram_size)) in radeon_bo_pin_restricted()
355 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; in radeon_bo_pin_restricted()
413 if (rdev->mc.igp_sideport_enabled == false) in radeon_bo_evict_vram()
446 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base, in radeon_bo_init()
447 rdev->mc.aper_size); in radeon_bo_init()
450 rdev->mc.mc_vram_size >> 20, in radeon_bo_init()
451 (unsigned long long)rdev->mc.aper_size >> 20); in radeon_bo_init()
453 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); in radeon_bo_init()
460 arch_phys_wc_del(rdev->mc.vram_mtrr); in radeon_bo_fini()
467 u64 real_vram_size = rdev->mc.real_vram_size; in radeon_bo_get_threshold_for_moves()
794 if ((offset + size) <= rdev->mc.visible_vram_size) in radeon_bo_fault_reserve_notify()
799 lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; in radeon_bo_fault_reserve_notify()
816 if ((offset + size) > rdev->mc.visible_vram_size) in radeon_bo_fault_reserve_notify()