41 	switch (rdev->mc.gtt_size/(1024*1024)) {  in rs400_gart_adjust_size()
52 			  (unsigned)(rdev->mc.gtt_size >> 20));  in rs400_gart_adjust_size()
55 		rdev->mc.gtt_size = 32 * 1024 * 1024;  in rs400_gart_adjust_size()
85 	switch(rdev->mc.gtt_size / (1024 * 1024)) {  in rs400_gart_init()
116 	switch(rdev->mc.gtt_size / (1024 * 1024)) {  in rs400_gart_enable()
149 	tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16);  in rs400_gart_enable()
150 	tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16);  in rs400_gart_enable()
188 		 (unsigned)(rdev->mc.gtt_size >> 20),  in rs400_gart_enable()
268 	rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev);  in rs400_mc_init()
270 	rdev->mc.vram_is_ddr = true;  in rs400_mc_init()
271 	rdev->mc.vram_width = 128;  in rs400_mc_init()
274 	radeon_vram_location(rdev, &rdev->mc, base);  in rs400_mc_init()
275 	rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;  in rs400_mc_init()
276 	radeon_gtt_location(rdev, &rdev->mc);  in rs400_mc_init()
399 		S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |  in rs400_mc_program()
400 		S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));  in rs400_mc_program()