Lines Matching refs:mc
590 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); in rs600_gart_enable()
591 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); in rs600_gart_enable()
595 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); in rs600_gart_enable()
596 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); in rs600_gart_enable()
605 (unsigned)(rdev->mc.gtt_size >> 20), in rs600_gart_enable()
868 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in rs600_mc_init()
869 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in rs600_mc_init()
870 rdev->mc.vram_is_ddr = true; in rs600_mc_init()
871 rdev->mc.vram_width = 128; in rs600_mc_init()
872 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); in rs600_mc_init()
873 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; in rs600_mc_init()
874 rdev->mc.visible_vram_size = rdev->mc.aper_size; in rs600_mc_init()
875 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); in rs600_mc_init()
878 radeon_vram_location(rdev, &rdev->mc, base); in rs600_mc_init()
879 rdev->mc.gtt_base_align = 0; in rs600_mc_init()
880 radeon_gtt_location(rdev, &rdev->mc); in rs600_mc_init()
968 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | in rs600_mc_program()
969 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); in rs600_mc_program()
971 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); in rs600_mc_program()