43 static const u32 crtc_offsets[2] =  variable
308 		crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;  in rv515_mc_stop()
311 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);  in rv515_mc_stop()
314 				WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);  in rv515_mc_stop()
316 				WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);  in rv515_mc_stop()
317 				WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);  in rv515_mc_stop()
328 			WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);  in rv515_mc_stop()
329 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);  in rv515_mc_stop()
331 			WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);  in rv515_mc_stop()
332 			WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);  in rv515_mc_stop()
364 			tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);  in rv515_mc_stop()
367 				WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);  in rv515_mc_stop()
369 			tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);  in rv515_mc_stop()
372 				WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);  in rv515_mc_stop()
398 		WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],  in rv515_mc_resume()
400 		WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],  in rv515_mc_resume()
408 			tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);  in rv515_mc_resume()
412 				WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);  in rv515_mc_resume()
414 			tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);  in rv515_mc_resume()
417 				WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);  in rv515_mc_resume()
419 			tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);  in rv515_mc_resume()
422 				WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);  in rv515_mc_resume()
425 				tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);  in rv515_mc_resume()
450 			tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);  in rv515_mc_resume()
452 			WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);  in rv515_mc_resume()