Lines Matching refs:BANK_WIDTH

2468 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |  in si_tiling_mode_table_init()
2478 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2488 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2498 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2508 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2518 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2528 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2538 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2548 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2558 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2568 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2578 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2588 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2598 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2608 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2618 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2628 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2638 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2648 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in si_tiling_mode_table_init()
2658 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2668 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2678 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2688 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2710 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2720 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2730 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2740 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2750 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2760 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2770 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2780 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2790 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2800 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2810 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2820 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2830 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2840 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2850 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2860 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2870 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2880 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2890 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) | in si_tiling_mode_table_init()
2900 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2910 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2920 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()
2930 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) | in si_tiling_mode_table_init()