Lines Matching refs:DMA1_REGISTER_OFFSET
1288 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET): in si_get_allowed_info_register()
3277 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); in si_gpu_init()
3801 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET); in si_gpu_check_soft_reset()
3884 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_soft_reset()
3886 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
4049 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in si_gpu_pci_config_reset()
4051 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
5525 offset = DMA1_REGISTER_OFFSET; in si_enable_dma_mgcg()
5537 offset = DMA1_REGISTER_OFFSET; in si_enable_dma_mgcg()
5943 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_disable_interrupt_state()
5944 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
6097 dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; in si_irq_set()
6184 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1); in si_irq_set()