1290 		*val = RREG32(reg);  in si_get_allowed_info_register()
1313 	tmp = RREG32(CG_CLKPIN_CNTL_2);  in si_get_xclk()
1317 	tmp = RREG32(CG_CLKPIN_CNTL);  in si_get_xclk()
1330 	temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>  in si_get_temp()
1593 	running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;  in si_mc_load_microcode()
1597 			blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);  in si_mc_load_microcode()
1630 			if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)  in si_mc_load_microcode()
1635 			if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)  in si_mc_load_microcode()
1950 		if (RREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &  in dce6_line_buffer_adjust()
1972 	u32 tmp = RREG32(MC_SHARED_CHMAP);  in si_get_number_of_dram_channels()
2382 	arb_control3 = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);  in dce6_program_watermarks()
2391 	tmp = RREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset);  in dce6_program_watermarks()
2976 	data = RREG32(CC_GC_SHADER_ARRAY_CONFIG);  in si_get_cu_enabled()
2981 	data |= RREG32(GC_USER_SHADER_ARRAY_CONFIG);  in si_get_cu_enabled()
3000 			data = RREG32(SPI_STATIC_THREAD_MGMT_3);  in si_setup_spi()
3023 	data = RREG32(CC_RB_BACKEND_DISABLE);  in si_get_rb_disabled()
3028 	data |= RREG32(GC_USER_RB_BACKEND_DISABLE);  in si_get_rb_disabled()
3202 	mc_shared_chmap = RREG32(MC_SHARED_CHMAP);  in si_gpu_init()
3203 	mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);  in si_gpu_init()
3307 	sx_debug_1 = RREG32(SX_DEBUG_1);  in si_gpu_init()
3341 	tmp = RREG32(HDP_MISC_CNTL);  in si_gpu_init()
3345 	hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);  in si_gpu_init()
3774 	tmp = RREG32(GRBM_STATUS);  in si_gpu_check_soft_reset()
3791 	tmp = RREG32(GRBM_STATUS2);  in si_gpu_check_soft_reset()
3796 	tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);  in si_gpu_check_soft_reset()
3801 	tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);  in si_gpu_check_soft_reset()
3806 	tmp = RREG32(SRBM_STATUS2);  in si_gpu_check_soft_reset()
3814 	tmp = RREG32(SRBM_STATUS);  in si_gpu_check_soft_reset()
3836 	tmp = RREG32(VM_L2_STATUS);  in si_gpu_check_soft_reset()
3862 		 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));  in si_gpu_soft_reset()
3864 		 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));  in si_gpu_soft_reset()
3878 		tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);  in si_gpu_soft_reset()
3884 		tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);  in si_gpu_soft_reset()
3945 		tmp = RREG32(GRBM_SOFT_RESET);  in si_gpu_soft_reset()
3949 		tmp = RREG32(GRBM_SOFT_RESET);  in si_gpu_soft_reset()
3955 		tmp = RREG32(GRBM_SOFT_RESET);  in si_gpu_soft_reset()
3959 		tmp = RREG32(SRBM_SOFT_RESET);  in si_gpu_soft_reset()
3963 		tmp = RREG32(SRBM_SOFT_RESET);  in si_gpu_soft_reset()
3969 		tmp = RREG32(SRBM_SOFT_RESET);  in si_gpu_soft_reset()
3985 	tmp = RREG32(CG_SPLL_FUNC_CNTL);  in si_set_clk_bypass_mode()
3989 	tmp = RREG32(CG_SPLL_FUNC_CNTL_2);  in si_set_clk_bypass_mode()
3994 		if (RREG32(SPLL_STATUS) & SPLL_CHG_STATUS)  in si_set_clk_bypass_mode()
3999 	tmp = RREG32(CG_SPLL_FUNC_CNTL_2);  in si_set_clk_bypass_mode()
4003 	tmp = RREG32(MPLL_CNTL_MODE);  in si_set_clk_bypass_mode()
4012 	tmp = RREG32(SPLL_CNTL_MODE);  in si_spll_powerdown()
4016 	tmp = RREG32(CG_SPLL_FUNC_CNTL);  in si_spll_powerdown()
4020 	tmp = RREG32(CG_SPLL_FUNC_CNTL);  in si_spll_powerdown()
4024 	tmp = RREG32(SPLL_CNTL_MODE);  in si_spll_powerdown()
4045 	tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);  in si_gpu_pci_config_reset()
4049 	tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);  in si_gpu_pci_config_reset()
4075 		if (RREG32(CONFIG_MEMSIZE) != 0xffffffff)  in si_gpu_pci_config_reset()
4202 	tmp = RREG32(MC_ARB_RAMCFG);  in si_mc_init()
4210 	tmp = RREG32(MC_SHARED_CHMAP);  in si_mc_init()
4246 	tmp = RREG32(CONFIG_MEMSIZE);  in si_mc_init()
4372 		rdev->vm_manager.saved_table_addr[i] = RREG32(reg);  in si_pcie_gart_disable()
5117 		if (RREG32(RLC_SERDES_MASTER_BUSY_0) == 0)  in si_wait_for_rlc_serdes()
5123 		if (RREG32(RLC_SERDES_MASTER_BUSY_1) == 0)  in si_wait_for_rlc_serdes()
5132 	u32 tmp = RREG32(CP_INT_CNTL_RING0);  in si_enable_gui_idle_interrupt()
5144 		tmp = RREG32(DB_DEPTH_INFO);  in si_enable_gui_idle_interrupt()
5148 			if ((RREG32(RLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))  in si_enable_gui_idle_interrupt()
5160 	tmp = RREG32(UVD_CGC_CTRL);  in si_set_uvd_dcm()
5183 		u32 tmp = RREG32(UVD_CGC_CTRL);  in si_init_uvd_internal_cg()
5193 	orig = data = RREG32(RLC_CNTL);  in si_halt_rlc()
5209 	tmp = RREG32(RLC_CNTL);  in si_update_rlc()
5218 	orig = data = RREG32(DMA_PG);  in si_enable_dma_pg()
5247 		tmp = RREG32(RLC_PG_CNTL);  in si_enable_gfx_cgpg()
5251 		tmp = RREG32(RLC_AUTO_PG_CTRL);  in si_enable_gfx_cgpg()
5255 		tmp = RREG32(RLC_AUTO_PG_CTRL);  in si_enable_gfx_cgpg()
5259 		tmp = RREG32(DB_RENDER_CONTROL);  in si_enable_gfx_cgpg()
5269 	tmp = RREG32(RLC_PG_CNTL);  in si_init_gfx_cgpg()
5275 	tmp = RREG32(RLC_AUTO_PG_CTRL);  in si_init_gfx_cgpg()
5289 	tmp = RREG32(CC_GC_SHADER_ARRAY_CONFIG);  in si_get_cu_active_bitmap()
5290 	tmp1 = RREG32(GC_USER_SHADER_ARRAY_CONFIG);  in si_get_cu_active_bitmap()
5333 	tmp = RREG32(RLC_MAX_PG_CU);  in si_init_ao_cu_mask()
5344 	orig = data = RREG32(RLC_CGCG_CGLS_CTRL);  in si_enable_cgcg()
5367 		RREG32(CB_CGTT_SCLK_CTRL);  in si_enable_cgcg()
5368 		RREG32(CB_CGTT_SCLK_CTRL);  in si_enable_cgcg()
5369 		RREG32(CB_CGTT_SCLK_CTRL);  in si_enable_cgcg()
5370 		RREG32(CB_CGTT_SCLK_CTRL);  in si_enable_cgcg()
5385 		orig = data = RREG32(CGTS_SM_CTRL_REG);  in si_enable_mgcg()
5391 			orig = data = RREG32(CP_MEM_SLP_CNTL);  in si_enable_mgcg()
5397 		orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);  in si_enable_mgcg()
5410 		orig = data = RREG32(RLC_CGTT_MGCG_OVERRIDE);  in si_enable_mgcg()
5415 		data = RREG32(CP_MEM_SLP_CNTL);  in si_enable_mgcg()
5420 		orig = data = RREG32(CGTS_SM_CTRL_REG);  in si_enable_mgcg()
5445 		orig = data = RREG32(UVD_CGC_CTRL);  in si_enable_uvd_mgcg()
5457 		orig = data = RREG32(UVD_CGC_CTRL);  in si_enable_uvd_mgcg()
5487 		orig = data = RREG32(mc_cg_registers[i]);  in si_enable_mc_ls()
5504 		orig = data = RREG32(mc_cg_registers[i]);  in si_enable_mc_mgcg()
5526 			orig = data = RREG32(DMA_POWER_CNTL + offset);  in si_enable_dma_mgcg()
5538 			orig = data = RREG32(DMA_POWER_CNTL + offset);  in si_enable_dma_mgcg()
5543 			orig = data = RREG32(DMA_CLK_CTRL + offset);  in si_enable_dma_mgcg()
5574 	orig = data = RREG32(HDP_HOST_PATH_CNTL);  in si_enable_hdp_mgcg()
5590 	orig = data = RREG32(HDP_MEM_POWER_LS);  in si_enable_hdp_ls()
5793 	u32 tmp = RREG32(GRBM_SOFT_RESET);  in si_rlc_reset()
5826 	tmp = RREG32(MC_SEQ_MISC0);  in si_lbpw_supported()
5836 	tmp = RREG32(RLC_LB_CNTL);  in si_enable_lbpw()
5906 	u32 ih_cntl = RREG32(IH_CNTL);  in si_enable_interrupts()
5907 	u32 ih_rb_cntl = RREG32(IH_RB_CNTL);  in si_enable_interrupts()
5918 	u32 ih_rb_cntl = RREG32(IH_RB_CNTL);  in si_disable_interrupts()
5919 	u32 ih_cntl = RREG32(IH_CNTL);  in si_disable_interrupts()
5936 	tmp = RREG32(CP_INT_CNTL_RING0) &  in si_disable_interrupt_state()
5941 	tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;  in si_disable_interrupt_state()
5943 	tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;  in si_disable_interrupt_state()
5976 		tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;  in si_disable_interrupt_state()
5978 		tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;  in si_disable_interrupt_state()
5980 		tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;  in si_disable_interrupt_state()
5982 		tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;  in si_disable_interrupt_state()
5984 		tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;  in si_disable_interrupt_state()
5986 		tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;  in si_disable_interrupt_state()
6015 	interrupt_cntl = RREG32(INTERRUPT_CNTL);  in si_irq_init()
6084 	cp_int_cntl = RREG32(CP_INT_CNTL_RING0) &  in si_irq_set()
6088 		hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);  in si_irq_set()
6089 		hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);  in si_irq_set()
6090 		hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);  in si_irq_set()
6091 		hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);  in si_irq_set()
6092 		hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);  in si_irq_set()
6093 		hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);  in si_irq_set()
6096 	dma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;  in si_irq_set()
6097 	dma_cntl1 = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;  in si_irq_set()
6099 	thermal_int = RREG32(CG_THERMAL_INT) &  in si_irq_set()
6237 	RREG32(SRBM_STATUS);  in si_irq_set()
6249 	rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);  in si_irq_ack()
6250 	rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);  in si_irq_ack()
6251 	rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);  in si_irq_ack()
6252 	rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);  in si_irq_ack()
6253 	rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);  in si_irq_ack()
6254 	rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);  in si_irq_ack()
6255 …rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSE…  in si_irq_ack()
6256 …rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSE…  in si_irq_ack()
6258 …rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSE…  in si_irq_ack()
6259 …rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSE…  in si_irq_ack()
6262 …rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSE…  in si_irq_ack()
6263 …rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSE…  in si_irq_ack()
6310 		tmp = RREG32(DC_HPD1_INT_CONTROL);  in si_irq_ack()
6315 		tmp = RREG32(DC_HPD2_INT_CONTROL);  in si_irq_ack()
6320 		tmp = RREG32(DC_HPD3_INT_CONTROL);  in si_irq_ack()
6325 		tmp = RREG32(DC_HPD4_INT_CONTROL);  in si_irq_ack()
6330 		tmp = RREG32(DC_HPD5_INT_CONTROL);  in si_irq_ack()
6335 		tmp = RREG32(DC_HPD5_INT_CONTROL);  in si_irq_ack()
6341 		tmp = RREG32(DC_HPD1_INT_CONTROL);  in si_irq_ack()
6346 		tmp = RREG32(DC_HPD2_INT_CONTROL);  in si_irq_ack()
6351 		tmp = RREG32(DC_HPD3_INT_CONTROL);  in si_irq_ack()
6356 		tmp = RREG32(DC_HPD4_INT_CONTROL);  in si_irq_ack()
6361 		tmp = RREG32(DC_HPD5_INT_CONTROL);  in si_irq_ack()
6366 		tmp = RREG32(DC_HPD5_INT_CONTROL);  in si_irq_ack()
6400 		wptr = RREG32(IH_RB_WPTR);  in si_get_ih_wptr()
6411 		tmp = RREG32(IH_RB_CNTL);  in si_get_ih_wptr()
6772 			DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));  in si_irq_process()
6781 			addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);  in si_irq_process()
6782 			status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);  in si_irq_process()
7267 	clock = (uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_LSB) |  in si_get_gpu_clock_counter()
7268 	        ((uint64_t)RREG32(RLC_GPU_CLOCK_COUNT_MSB) << 32ULL);  in si_get_gpu_clock_counter()
7669 				orig = data = RREG32(THM_CLK_CNTL);  in si_program_aspm()
7675 				orig = data = RREG32(MISC_CLK_CNTL);  in si_program_aspm()
7681 				orig = data = RREG32(CG_CLKPIN_CNTL);  in si_program_aspm()
7686 				orig = data = RREG32(CG_CLKPIN_CNTL_2);  in si_program_aspm()
7691 				orig = data = RREG32(MPLL_BYPASSCLK_SEL);  in si_program_aspm()
7697 				orig = data = RREG32(SPLL_CNTL_MODE);  in si_program_aspm()