Lines Matching refs:WREG32
1598 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1); in si_mc_load_microcode()
1602 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in si_mc_load_microcode()
1603 WREG32(MC_SEQ_SUP_CNTL, 0x00000010); in si_mc_load_microcode()
1608 WREG32(MC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++)); in si_mc_load_microcode()
1609 WREG32(MC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++)); in si_mc_load_microcode()
1611 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]); in si_mc_load_microcode()
1612 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]); in si_mc_load_microcode()
1618 WREG32(MC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++)); in si_mc_load_microcode()
1620 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++)); in si_mc_load_microcode()
1624 WREG32(MC_SEQ_SUP_CNTL, 0x00000008); in si_mc_load_microcode()
1625 WREG32(MC_SEQ_SUP_CNTL, 0x00000004); in si_mc_load_microcode()
1626 WREG32(MC_SEQ_SUP_CNTL, 0x00000001); in si_mc_load_microcode()
1641 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout); in si_mc_load_microcode()
1944 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, in dce6_line_buffer_adjust()
1947 WREG32(PIPE0_DMIF_BUFFER_CONTROL + pipe_offset, in dce6_line_buffer_adjust()
2386 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); in dce6_program_watermarks()
2387 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce6_program_watermarks()
2394 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, tmp); in dce6_program_watermarks()
2395 WREG32(DPG_PIPE_LATENCY_CONTROL + radeon_crtc->crtc_offset, in dce6_program_watermarks()
2399 WREG32(DPG_PIPE_ARBITRATION_CONTROL3 + radeon_crtc->crtc_offset, arb_control3); in dce6_program_watermarks()
2402 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt); in dce6_program_watermarks()
2403 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt); in dce6_program_watermarks()
2697 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in si_tiling_mode_table_init()
2939 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in si_tiling_mode_table_init()
2958 WREG32(GRBM_GFX_INDEX, data); in si_select_se_sh()
3008 WREG32(SPI_STATIC_THREAD_MGMT_3, data); in si_setup_spi()
3082 WREG32(PA_SC_RASTER_CONFIG, data); in si_setup_rb()
3187 WREG32((0x2c14 + j), 0x00000000); in si_gpu_init()
3188 WREG32((0x2c18 + j), 0x00000000); in si_gpu_init()
3189 WREG32((0x2c1c + j), 0x00000000); in si_gpu_init()
3190 WREG32((0x2c20 + j), 0x00000000); in si_gpu_init()
3191 WREG32((0x2c24 + j), 0x00000000); in si_gpu_init()
3194 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); in si_gpu_init()
3195 WREG32(SRBM_INT_CNTL, 1); in si_gpu_init()
3196 WREG32(SRBM_INT_ACK, 1); in si_gpu_init()
3200 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); in si_gpu_init()
3272 WREG32(GB_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3273 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3274 WREG32(DMIF_ADDR_CALC, gb_addr_config); in si_gpu_init()
3275 WREG32(HDP_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3276 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config); in si_gpu_init()
3277 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config); in si_gpu_init()
3279 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3280 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3281 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config); in si_gpu_init()
3303 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | in si_gpu_init()
3305 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); in si_gpu_init()
3308 WREG32(SX_DEBUG_1, sx_debug_1); in si_gpu_init()
3310 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); in si_gpu_init()
3312 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) | in si_gpu_init()
3317 WREG32(VGT_NUM_INSTANCES, 1); in si_gpu_init()
3319 WREG32(CP_PERFMON_CNTL, 0); in si_gpu_init()
3321 WREG32(SQ_CONFIG, 0); in si_gpu_init()
3323 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | in si_gpu_init()
3326 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) | in si_gpu_init()
3329 WREG32(VGT_GS_VERTEX_REUSE, 16); in si_gpu_init()
3330 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); in si_gpu_init()
3332 WREG32(CB_PERFCOUNTER0_SELECT0, 0); in si_gpu_init()
3333 WREG32(CB_PERFCOUNTER0_SELECT1, 0); in si_gpu_init()
3334 WREG32(CB_PERFCOUNTER1_SELECT0, 0); in si_gpu_init()
3335 WREG32(CB_PERFCOUNTER1_SELECT1, 0); in si_gpu_init()
3336 WREG32(CB_PERFCOUNTER2_SELECT0, 0); in si_gpu_init()
3337 WREG32(CB_PERFCOUNTER2_SELECT1, 0); in si_gpu_init()
3338 WREG32(CB_PERFCOUNTER3_SELECT0, 0); in si_gpu_init()
3339 WREG32(CB_PERFCOUNTER3_SELECT1, 0); in si_gpu_init()
3343 WREG32(HDP_MISC_CNTL, tmp); in si_gpu_init()
3346 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); in si_gpu_init()
3348 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3)); in si_gpu_init()
3461 WREG32(CP_ME_CNTL, 0); in si_cp_enable()
3465 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); in si_cp_enable()
3466 WREG32(SCRATCH_UMSK, 0); in si_cp_enable()
3501 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3503 WREG32(CP_PFP_UCODE_DATA, le32_to_cpup(fw_data++)); in si_cp_load_microcode()
3504 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3510 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3512 WREG32(CP_CE_UCODE_DATA, le32_to_cpup(fw_data++)); in si_cp_load_microcode()
3513 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3519 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3521 WREG32(CP_ME_RAM_DATA, le32_to_cpup(fw_data++)); in si_cp_load_microcode()
3522 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3528 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3530 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); in si_cp_load_microcode()
3531 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3535 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3537 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++)); in si_cp_load_microcode()
3538 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3542 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3544 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); in si_cp_load_microcode()
3545 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3548 WREG32(CP_PFP_UCODE_ADDR, 0); in si_cp_load_microcode()
3549 WREG32(CP_CE_UCODE_ADDR, 0); in si_cp_load_microcode()
3550 WREG32(CP_ME_RAM_WADDR, 0); in si_cp_load_microcode()
3551 WREG32(CP_ME_RAM_RADDR, 0); in si_cp_load_microcode()
3651 WREG32(CP_SEM_WAIT_TIMER, 0x0); in si_cp_resume()
3652 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0); in si_cp_resume()
3655 WREG32(CP_RB_WPTR_DELAY, 0); in si_cp_resume()
3657 WREG32(CP_DEBUG, 0); in si_cp_resume()
3658 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in si_cp_resume()
3668 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
3671 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3673 WREG32(CP_RB0_WPTR, ring->wptr); in si_cp_resume()
3676 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); in si_cp_resume()
3677 WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in si_cp_resume()
3680 WREG32(SCRATCH_UMSK, 0xff); in si_cp_resume()
3683 WREG32(SCRATCH_UMSK, 0); in si_cp_resume()
3687 WREG32(CP_RB0_CNTL, tmp); in si_cp_resume()
3689 WREG32(CP_RB0_BASE, ring->gpu_addr >> 8); in si_cp_resume()
3699 WREG32(CP_RB1_CNTL, tmp); in si_cp_resume()
3702 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3704 WREG32(CP_RB1_WPTR, ring->wptr); in si_cp_resume()
3707 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); in si_cp_resume()
3708 WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF); in si_cp_resume()
3711 WREG32(CP_RB1_CNTL, tmp); in si_cp_resume()
3713 WREG32(CP_RB1_BASE, ring->gpu_addr >> 8); in si_cp_resume()
3723 WREG32(CP_RB2_CNTL, tmp); in si_cp_resume()
3726 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); in si_cp_resume()
3728 WREG32(CP_RB2_WPTR, ring->wptr); in si_cp_resume()
3731 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); in si_cp_resume()
3732 WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF); in si_cp_resume()
3735 WREG32(CP_RB2_CNTL, tmp); in si_cp_resume()
3737 WREG32(CP_RB2_BASE, ring->gpu_addr >> 8); in si_cp_resume()
3874 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in si_gpu_soft_reset()
3880 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
3886 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_soft_reset()
3948 WREG32(GRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3954 WREG32(GRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3962 WREG32(SRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3968 WREG32(SRBM_SOFT_RESET, tmp); in si_gpu_soft_reset()
3987 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_set_clk_bypass_mode()
3991 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
4001 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); in si_set_clk_bypass_mode()
4005 WREG32(MPLL_CNTL_MODE, tmp); in si_set_clk_bypass_mode()
4014 WREG32(SPLL_CNTL_MODE, tmp); in si_spll_powerdown()
4018 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
4022 WREG32(CG_SPLL_FUNC_CNTL, tmp); in si_spll_powerdown()
4026 WREG32(SPLL_CNTL_MODE, tmp); in si_spll_powerdown()
4043 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in si_gpu_pci_config_reset()
4047 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
4051 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_gpu_pci_config_reset()
4138 WREG32((0x2c14 + j), 0x00000000); in si_mc_program()
4139 WREG32((0x2c18 + j), 0x00000000); in si_mc_program()
4140 WREG32((0x2c1c + j), 0x00000000); in si_mc_program()
4141 WREG32((0x2c20 + j), 0x00000000); in si_mc_program()
4142 WREG32((0x2c24 + j), 0x00000000); in si_mc_program()
4144 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); in si_mc_program()
4152 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); in si_mc_program()
4154 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in si_mc_program()
4156 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in si_mc_program()
4158 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, in si_mc_program()
4162 WREG32(MC_VM_FB_LOCATION, tmp); in si_mc_program()
4164 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in si_mc_program()
4165 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30)); in si_mc_program()
4166 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); in si_mc_program()
4167 WREG32(MC_VM_AGP_BASE, 0); in si_mc_program()
4168 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); in si_mc_program()
4169 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); in si_mc_program()
4268 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); in si_pcie_gart_tlb_flush()
4271 WREG32(VM_INVALIDATE_REQUEST, 1); in si_pcie_gart_tlb_flush()
4286 WREG32(MC_VM_MX_L1_TLB_CNTL, in si_pcie_gart_enable()
4294 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in si_pcie_gart_enable()
4300 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE); in si_pcie_gart_enable()
4301 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in si_pcie_gart_enable()
4305 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in si_pcie_gart_enable()
4306 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in si_pcie_gart_enable()
4307 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in si_pcie_gart_enable()
4308 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, in si_pcie_gart_enable()
4310 WREG32(VM_CONTEXT0_CNTL2, 0); in si_pcie_gart_enable()
4311 WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | in si_pcie_gart_enable()
4314 WREG32(0x15D4, 0); in si_pcie_gart_enable()
4315 WREG32(0x15D8, 0); in si_pcie_gart_enable()
4316 WREG32(0x15DC, 0); in si_pcie_gart_enable()
4320 WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0); in si_pcie_gart_enable()
4321 WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn - 1); in si_pcie_gart_enable()
4328 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2), in si_pcie_gart_enable()
4331 WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2), in si_pcie_gart_enable()
4336 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR, in si_pcie_gart_enable()
4338 WREG32(VM_CONTEXT1_CNTL2, 4); in si_pcie_gart_enable()
4339 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) | in si_pcie_gart_enable()
4376 WREG32(VM_CONTEXT0_CNTL, 0); in si_pcie_gart_disable()
4377 WREG32(VM_CONTEXT1_CNTL, 0); in si_pcie_gart_disable()
4379 WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS | in si_pcie_gart_disable()
4382 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | in si_pcie_gart_disable()
4386 WREG32(VM_L2_CNTL2, 0); in si_pcie_gart_disable()
4387 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY | in si_pcie_gart_disable()
5140 WREG32(CP_INT_CNTL_RING0, tmp); in si_enable_gui_idle_interrupt()
5172 WREG32(UVD_CGC_CTRL, tmp); in si_set_uvd_dcm()
5185 WREG32(UVD_CGC_CTRL, tmp); in si_init_uvd_internal_cg()
5197 WREG32(RLC_CNTL, data); in si_halt_rlc()
5211 WREG32(RLC_CNTL, rlc); in si_update_rlc()
5224 WREG32(DMA_PG, data); in si_enable_dma_pg()
5231 WREG32(DMA_PGFSM_WRITE, 0x00002000); in si_init_dma_pg()
5232 WREG32(DMA_PGFSM_CONFIG, 0x100010ff); in si_init_dma_pg()
5235 WREG32(DMA_PGFSM_WRITE, 0); in si_init_dma_pg()
5245 WREG32(RLC_TTOP_D, tmp); in si_enable_gfx_cgpg()
5249 WREG32(RLC_PG_CNTL, tmp); in si_enable_gfx_cgpg()
5253 WREG32(RLC_AUTO_PG_CTRL, tmp); in si_enable_gfx_cgpg()
5257 WREG32(RLC_AUTO_PG_CTRL, tmp); in si_enable_gfx_cgpg()
5267 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_gfx_cgpg()
5271 WREG32(RLC_PG_CNTL, tmp); in si_init_gfx_cgpg()
5273 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_gfx_cgpg()
5280 WREG32(RLC_AUTO_PG_CTRL, tmp); in si_init_gfx_cgpg()
5331 WREG32(RLC_PG_AO_CU_MASK, tmp); in si_init_ao_cu_mask()
5336 WREG32(RLC_MAX_PG_CU, tmp); in si_init_ao_cu_mask()
5349 WREG32(RLC_GCPM_GENERAL_3, 0x00000080); in si_enable_cgcg()
5353 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); in si_enable_cgcg()
5354 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); in si_enable_cgcg()
5355 WREG32(RLC_SERDES_WR_CTRL, 0x00b000ff); in si_enable_cgcg()
5361 WREG32(RLC_SERDES_WR_CTRL, 0x007000ff); in si_enable_cgcg()
5376 WREG32(RLC_CGCG_CGLS_CTRL, data); in si_enable_cgcg()
5388 WREG32(CGTS_SM_CTRL_REG, data); in si_enable_mgcg()
5394 WREG32(CP_MEM_SLP_CNTL, data); in si_enable_mgcg()
5400 WREG32(RLC_CGTT_MGCG_OVERRIDE, data); in si_enable_mgcg()
5404 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); in si_enable_mgcg()
5405 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); in si_enable_mgcg()
5406 WREG32(RLC_SERDES_WR_CTRL, 0x00d000ff); in si_enable_mgcg()
5413 WREG32(RLC_CGTT_MGCG_OVERRIDE, data); in si_enable_mgcg()
5418 WREG32(CP_MEM_SLP_CNTL, data); in si_enable_mgcg()
5423 WREG32(CGTS_SM_CTRL_REG, data); in si_enable_mgcg()
5427 WREG32(RLC_SERDES_WR_MASTER_MASK_0, 0xffffffff); in si_enable_mgcg()
5428 WREG32(RLC_SERDES_WR_MASTER_MASK_1, 0xffffffff); in si_enable_mgcg()
5429 WREG32(RLC_SERDES_WR_CTRL, 0x00e000ff); in si_enable_mgcg()
5448 WREG32(UVD_CGC_CTRL, data); in si_enable_uvd_mgcg()
5460 WREG32(UVD_CGC_CTRL, data); in si_enable_uvd_mgcg()
5493 WREG32(mc_cg_registers[i], data); in si_enable_mc_ls()
5510 WREG32(mc_cg_registers[i], data); in si_enable_mc_mgcg()
5529 WREG32(DMA_POWER_CNTL + offset, data); in si_enable_dma_mgcg()
5530 WREG32(DMA_CLK_CTRL + offset, 0x00000100); in si_enable_dma_mgcg()
5541 WREG32(DMA_POWER_CNTL + offset, data); in si_enable_dma_mgcg()
5546 WREG32(DMA_CLK_CTRL + offset, data); in si_enable_dma_mgcg()
5582 WREG32(HDP_HOST_PATH_CNTL, data); in si_enable_hdp_mgcg()
5598 WREG32(HDP_MEM_POWER_LS, data); in si_enable_hdp_ls()
5769 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_pg()
5770 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
5775 WREG32(RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in si_init_pg()
5776 WREG32(RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in si_init_pg()
5796 WREG32(GRBM_SOFT_RESET, tmp); in si_rlc_reset()
5799 WREG32(GRBM_SOFT_RESET, tmp); in si_rlc_reset()
5805 WREG32(RLC_CNTL, 0); in si_rlc_stop()
5814 WREG32(RLC_CNTL, RLC_ENABLE); in si_rlc_start()
5841 WREG32(RLC_LB_CNTL, tmp); in si_enable_lbpw()
5845 WREG32(SPI_LB_CU_MASK, 0x00ff); in si_enable_lbpw()
5864 WREG32(RLC_RL_BASE, 0); in si_rlc_resume()
5865 WREG32(RLC_RL_SIZE, 0); in si_rlc_resume()
5866 WREG32(RLC_LB_CNTL, 0); in si_rlc_resume()
5867 WREG32(RLC_LB_CNTR_MAX, 0xffffffff); in si_rlc_resume()
5868 WREG32(RLC_LB_CNTR_INIT, 0); in si_rlc_resume()
5869 WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff); in si_rlc_resume()
5871 WREG32(RLC_MC_CNTL, 0); in si_rlc_resume()
5872 WREG32(RLC_UCODE_CNTL, 0); in si_rlc_resume()
5884 WREG32(RLC_UCODE_ADDR, i); in si_rlc_resume()
5885 WREG32(RLC_UCODE_DATA, le32_to_cpup(fw_data++)); in si_rlc_resume()
5891 WREG32(RLC_UCODE_ADDR, i); in si_rlc_resume()
5892 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); in si_rlc_resume()
5895 WREG32(RLC_UCODE_ADDR, 0); in si_rlc_resume()
5911 WREG32(IH_CNTL, ih_cntl); in si_enable_interrupts()
5912 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_enable_interrupts()
5923 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_disable_interrupts()
5924 WREG32(IH_CNTL, ih_cntl); in si_disable_interrupts()
5926 WREG32(IH_RB_RPTR, 0); in si_disable_interrupts()
5927 WREG32(IH_RB_WPTR, 0); in si_disable_interrupts()
5938 WREG32(CP_INT_CNTL_RING0, tmp); in si_disable_interrupt_state()
5939 WREG32(CP_INT_CNTL_RING1, 0); in si_disable_interrupt_state()
5940 WREG32(CP_INT_CNTL_RING2, 0); in si_disable_interrupt_state()
5942 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
5944 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); in si_disable_interrupt_state()
5945 WREG32(GRBM_INT_CNTL, 0); in si_disable_interrupt_state()
5946 WREG32(SRBM_INT_CNTL, 0); in si_disable_interrupt_state()
5948 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5949 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5952 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5953 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5956 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5957 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5961 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5962 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5965 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5966 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5969 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5970 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in si_disable_interrupt_state()
5974 WREG32(DAC_AUTODETECT_INT_CONTROL, 0); in si_disable_interrupt_state()
5977 WREG32(DC_HPD1_INT_CONTROL, tmp); in si_disable_interrupt_state()
5979 WREG32(DC_HPD2_INT_CONTROL, tmp); in si_disable_interrupt_state()
5981 WREG32(DC_HPD3_INT_CONTROL, tmp); in si_disable_interrupt_state()
5983 WREG32(DC_HPD4_INT_CONTROL, tmp); in si_disable_interrupt_state()
5985 WREG32(DC_HPD5_INT_CONTROL, tmp); in si_disable_interrupt_state()
5987 WREG32(DC_HPD6_INT_CONTROL, tmp); in si_disable_interrupt_state()
6014 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8); in si_irq_init()
6022 WREG32(INTERRUPT_CNTL, interrupt_cntl); in si_irq_init()
6024 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8); in si_irq_init()
6035 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC); in si_irq_init()
6036 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF); in si_irq_init()
6038 WREG32(IH_RB_CNTL, ih_rb_cntl); in si_irq_init()
6041 WREG32(IH_RB_RPTR, 0); in si_irq_init()
6042 WREG32(IH_RB_WPTR, 0); in si_irq_init()
6049 WREG32(IH_CNTL, ih_cntl); in si_irq_init()
6179 WREG32(CP_INT_CNTL_RING0, cp_int_cntl); in si_irq_set()
6180 WREG32(CP_INT_CNTL_RING1, cp_int_cntl1); in si_irq_set()
6181 WREG32(CP_INT_CNTL_RING2, cp_int_cntl2); in si_irq_set()
6183 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, dma_cntl); in si_irq_set()
6184 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, dma_cntl1); in si_irq_set()
6186 WREG32(GRBM_INT_CNTL, grbm_int_cntl); in si_irq_set()
6194 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); in si_irq_set()
6195 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); in si_irq_set()
6198 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); in si_irq_set()
6199 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); in si_irq_set()
6202 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); in si_irq_set()
6203 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); in si_irq_set()
6207 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, in si_irq_set()
6209 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, in si_irq_set()
6213 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, in si_irq_set()
6215 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, in si_irq_set()
6219 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, in si_irq_set()
6221 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, in si_irq_set()
6226 WREG32(DC_HPD1_INT_CONTROL, hpd1); in si_irq_set()
6227 WREG32(DC_HPD2_INT_CONTROL, hpd2); in si_irq_set()
6228 WREG32(DC_HPD3_INT_CONTROL, hpd3); in si_irq_set()
6229 WREG32(DC_HPD4_INT_CONTROL, hpd4); in si_irq_set()
6230 WREG32(DC_HPD5_INT_CONTROL, hpd5); in si_irq_set()
6231 WREG32(DC_HPD6_INT_CONTROL, hpd6); in si_irq_set()
6234 WREG32(CG_THERMAL_INT, thermal_int); in si_irq_set()
6267 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in si_irq_ack()
6269 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in si_irq_ack()
6271 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); in si_irq_ack()
6273 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); in si_irq_ack()
6275 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); in si_irq_ack()
6277 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); in si_irq_ack()
6281 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in si_irq_ack()
6283 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in si_irq_ack()
6285 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); in si_irq_ack()
6287 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); in si_irq_ack()
6289 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); in si_irq_ack()
6291 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); in si_irq_ack()
6296 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in si_irq_ack()
6298 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR); in si_irq_ack()
6300 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); in si_irq_ack()
6302 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); in si_irq_ack()
6304 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); in si_irq_ack()
6306 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); in si_irq_ack()
6312 WREG32(DC_HPD1_INT_CONTROL, tmp); in si_irq_ack()
6317 WREG32(DC_HPD2_INT_CONTROL, tmp); in si_irq_ack()
6322 WREG32(DC_HPD3_INT_CONTROL, tmp); in si_irq_ack()
6327 WREG32(DC_HPD4_INT_CONTROL, tmp); in si_irq_ack()
6332 WREG32(DC_HPD5_INT_CONTROL, tmp); in si_irq_ack()
6337 WREG32(DC_HPD6_INT_CONTROL, tmp); in si_irq_ack()
6343 WREG32(DC_HPD1_INT_CONTROL, tmp); in si_irq_ack()
6348 WREG32(DC_HPD2_INT_CONTROL, tmp); in si_irq_ack()
6353 WREG32(DC_HPD3_INT_CONTROL, tmp); in si_irq_ack()
6358 WREG32(DC_HPD4_INT_CONTROL, tmp); in si_irq_ack()
6363 WREG32(DC_HPD5_INT_CONTROL, tmp); in si_irq_ack()
6368 WREG32(DC_HPD6_INT_CONTROL, tmp); in si_irq_ack()
6413 WREG32(IH_RB_CNTL, tmp); in si_get_ih_wptr()
6773 WREG32(SRBM_INT_ACK, 0x1); in si_irq_process()
6846 WREG32(IH_RB_RPTR, rptr); in si_irq_process()
7266 WREG32(RLC_CAPTURE_GPU_CLOCK_COUNT, 1); in si_get_gpu_clock_counter()
7673 WREG32(THM_CLK_CNTL, data); in si_program_aspm()
7679 WREG32(MISC_CLK_CNTL, data); in si_program_aspm()
7684 WREG32(CG_CLKPIN_CNTL, data); in si_program_aspm()
7689 WREG32(CG_CLKPIN_CNTL_2, data); in si_program_aspm()
7695 WREG32(MPLL_BYPASSCLK_SEL, data); in si_program_aspm()
7700 WREG32(SPLL_CNTL_MODE, data); in si_program_aspm()