3770 	u32 reset_mask = 0;  in si_gpu_check_soft_reset()  local
3781 		reset_mask |= RADEON_RESET_GFX;  in si_gpu_check_soft_reset()
3785 		reset_mask |= RADEON_RESET_CP;  in si_gpu_check_soft_reset()
3788 		reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;  in si_gpu_check_soft_reset()
3793 		reset_mask |= RADEON_RESET_RLC;  in si_gpu_check_soft_reset()
3798 		reset_mask |= RADEON_RESET_DMA;  in si_gpu_check_soft_reset()
3803 		reset_mask |= RADEON_RESET_DMA1;  in si_gpu_check_soft_reset()
3808 		reset_mask |= RADEON_RESET_DMA;  in si_gpu_check_soft_reset()
3811 		reset_mask |= RADEON_RESET_DMA1;  in si_gpu_check_soft_reset()
3817 		reset_mask |= RADEON_RESET_IH;  in si_gpu_check_soft_reset()
3820 		reset_mask |= RADEON_RESET_SEM;  in si_gpu_check_soft_reset()
3823 		reset_mask |= RADEON_RESET_GRBM;  in si_gpu_check_soft_reset()
3826 		reset_mask |= RADEON_RESET_VMC;  in si_gpu_check_soft_reset()
3830 		reset_mask |= RADEON_RESET_MC;  in si_gpu_check_soft_reset()
3833 		reset_mask |= RADEON_RESET_DISPLAY;  in si_gpu_check_soft_reset()
3838 		reset_mask |= RADEON_RESET_VMC;  in si_gpu_check_soft_reset()
3841 	if (reset_mask & RADEON_RESET_MC) {  in si_gpu_check_soft_reset()
3842 		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);  in si_gpu_check_soft_reset()
3843 		reset_mask &= ~RADEON_RESET_MC;  in si_gpu_check_soft_reset()
3846 	return reset_mask;  in si_gpu_check_soft_reset()
3849 static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)  in si_gpu_soft_reset()  argument
3855 	if (reset_mask == 0)  in si_gpu_soft_reset()
3858 	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);  in si_gpu_soft_reset()
3876 	if (reset_mask & RADEON_RESET_DMA) {  in si_gpu_soft_reset()
3882 	if (reset_mask & RADEON_RESET_DMA1) {  in si_gpu_soft_reset()
3896 	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {  in si_gpu_soft_reset()
3911 	if (reset_mask & RADEON_RESET_CP) {  in si_gpu_soft_reset()
3917 	if (reset_mask & RADEON_RESET_DMA)  in si_gpu_soft_reset()
3920 	if (reset_mask & RADEON_RESET_DMA1)  in si_gpu_soft_reset()
3923 	if (reset_mask & RADEON_RESET_DISPLAY)  in si_gpu_soft_reset()
3926 	if (reset_mask & RADEON_RESET_RLC)  in si_gpu_soft_reset()
3929 	if (reset_mask & RADEON_RESET_SEM)  in si_gpu_soft_reset()
3932 	if (reset_mask & RADEON_RESET_IH)  in si_gpu_soft_reset()
3935 	if (reset_mask & RADEON_RESET_GRBM)  in si_gpu_soft_reset()
3938 	if (reset_mask & RADEON_RESET_VMC)  in si_gpu_soft_reset()
3941 	if (reset_mask & RADEON_RESET_MC)  in si_gpu_soft_reset()
4083 	u32 reset_mask;  in si_asic_reset()  local
4085 	reset_mask = si_gpu_check_soft_reset(rdev);  in si_asic_reset()
4087 	if (reset_mask)  in si_asic_reset()
4091 	si_gpu_soft_reset(rdev, reset_mask);  in si_asic_reset()
4093 	reset_mask = si_gpu_check_soft_reset(rdev);  in si_asic_reset()
4096 	if (reset_mask && radeon_hard_reset)  in si_asic_reset()
4099 	reset_mask = si_gpu_check_soft_reset(rdev);  in si_asic_reset()
4101 	if (!reset_mask)  in si_asic_reset()
4118 	u32 reset_mask = si_gpu_check_soft_reset(rdev);  in si_gfx_is_lockup()  local
4120 	if (!(reset_mask & (RADEON_RESET_GFX |  in si_gfx_is_lockup()