Lines Matching refs:si
2445 switch (rdev->config.si.mem_row_size_in_kb) { in si_tiling_mode_table_init()
2696 rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden; in si_tiling_mode_table_init()
2938 rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden; in si_tiling_mode_table_init()
3062 rdev->config.si.backend_enable_mask = enabled_rbs; in si_setup_rb()
3098 rdev->config.si.max_shader_engines = 2; in si_gpu_init()
3099 rdev->config.si.max_tile_pipes = 12; in si_gpu_init()
3100 rdev->config.si.max_cu_per_sh = 8; in si_gpu_init()
3101 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3102 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()
3103 rdev->config.si.max_texture_channel_caches = 12; in si_gpu_init()
3104 rdev->config.si.max_gprs = 256; in si_gpu_init()
3105 rdev->config.si.max_gs_threads = 32; in si_gpu_init()
3106 rdev->config.si.max_hw_contexts = 8; in si_gpu_init()
3108 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; in si_gpu_init()
3109 rdev->config.si.sc_prim_fifo_size_backend = 0x100; in si_gpu_init()
3110 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; in si_gpu_init()
3111 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; in si_gpu_init()
3115 rdev->config.si.max_shader_engines = 2; in si_gpu_init()
3116 rdev->config.si.max_tile_pipes = 8; in si_gpu_init()
3117 rdev->config.si.max_cu_per_sh = 5; in si_gpu_init()
3118 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3119 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()
3120 rdev->config.si.max_texture_channel_caches = 8; in si_gpu_init()
3121 rdev->config.si.max_gprs = 256; in si_gpu_init()
3122 rdev->config.si.max_gs_threads = 32; in si_gpu_init()
3123 rdev->config.si.max_hw_contexts = 8; in si_gpu_init()
3125 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; in si_gpu_init()
3126 rdev->config.si.sc_prim_fifo_size_backend = 0x100; in si_gpu_init()
3127 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; in si_gpu_init()
3128 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; in si_gpu_init()
3133 rdev->config.si.max_shader_engines = 1; in si_gpu_init()
3134 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()
3135 rdev->config.si.max_cu_per_sh = 5; in si_gpu_init()
3136 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3137 rdev->config.si.max_backends_per_se = 4; in si_gpu_init()
3138 rdev->config.si.max_texture_channel_caches = 4; in si_gpu_init()
3139 rdev->config.si.max_gprs = 256; in si_gpu_init()
3140 rdev->config.si.max_gs_threads = 32; in si_gpu_init()
3141 rdev->config.si.max_hw_contexts = 8; in si_gpu_init()
3143 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; in si_gpu_init()
3144 rdev->config.si.sc_prim_fifo_size_backend = 0x40; in si_gpu_init()
3145 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; in si_gpu_init()
3146 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; in si_gpu_init()
3150 rdev->config.si.max_shader_engines = 1; in si_gpu_init()
3151 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()
3152 rdev->config.si.max_cu_per_sh = 6; in si_gpu_init()
3153 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()
3154 rdev->config.si.max_backends_per_se = 2; in si_gpu_init()
3155 rdev->config.si.max_texture_channel_caches = 4; in si_gpu_init()
3156 rdev->config.si.max_gprs = 256; in si_gpu_init()
3157 rdev->config.si.max_gs_threads = 16; in si_gpu_init()
3158 rdev->config.si.max_hw_contexts = 8; in si_gpu_init()
3160 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; in si_gpu_init()
3161 rdev->config.si.sc_prim_fifo_size_backend = 0x40; in si_gpu_init()
3162 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; in si_gpu_init()
3163 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; in si_gpu_init()
3167 rdev->config.si.max_shader_engines = 1; in si_gpu_init()
3168 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()
3169 rdev->config.si.max_cu_per_sh = 5; in si_gpu_init()
3170 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()
3171 rdev->config.si.max_backends_per_se = 1; in si_gpu_init()
3172 rdev->config.si.max_texture_channel_caches = 2; in si_gpu_init()
3173 rdev->config.si.max_gprs = 256; in si_gpu_init()
3174 rdev->config.si.max_gs_threads = 16; in si_gpu_init()
3175 rdev->config.si.max_hw_contexts = 8; in si_gpu_init()
3177 rdev->config.si.sc_prim_fifo_size_frontend = 0x20; in si_gpu_init()
3178 rdev->config.si.sc_prim_fifo_size_backend = 0x40; in si_gpu_init()
3179 rdev->config.si.sc_hiz_tile_fifo_size = 0x30; in si_gpu_init()
3180 rdev->config.si.sc_earlyz_tile_fifo_size = 0x130; in si_gpu_init()
3205 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes; in si_gpu_init()
3206 rdev->config.si.mem_max_burst_length_bytes = 256; in si_gpu_init()
3208 rdev->config.si.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in si_gpu_init()
3209 if (rdev->config.si.mem_row_size_in_kb > 4) in si_gpu_init()
3210 rdev->config.si.mem_row_size_in_kb = 4; in si_gpu_init()
3212 rdev->config.si.shader_engine_tile_size = 32; in si_gpu_init()
3213 rdev->config.si.num_gpus = 1; in si_gpu_init()
3214 rdev->config.si.multi_gpu_tile_size = 64; in si_gpu_init()
3218 switch (rdev->config.si.mem_row_size_in_kb) { in si_gpu_init()
3238 rdev->config.si.tile_config = 0; in si_gpu_init()
3239 switch (rdev->config.si.num_tile_pipes) { in si_gpu_init()
3241 rdev->config.si.tile_config |= (0 << 0); in si_gpu_init()
3244 rdev->config.si.tile_config |= (1 << 0); in si_gpu_init()
3247 rdev->config.si.tile_config |= (2 << 0); in si_gpu_init()
3252 rdev->config.si.tile_config |= (3 << 0); in si_gpu_init()
3257 rdev->config.si.tile_config |= 0 << 4; in si_gpu_init()
3260 rdev->config.si.tile_config |= 1 << 4; in si_gpu_init()
3264 rdev->config.si.tile_config |= 2 << 4; in si_gpu_init()
3267 rdev->config.si.tile_config |= in si_gpu_init()
3269 rdev->config.si.tile_config |= in si_gpu_init()
3286 si_setup_rb(rdev, rdev->config.si.max_shader_engines, in si_gpu_init()
3287 rdev->config.si.max_sh_per_se, in si_gpu_init()
3288 rdev->config.si.max_backends_per_se); in si_gpu_init()
3290 si_setup_spi(rdev, rdev->config.si.max_shader_engines, in si_gpu_init()
3291 rdev->config.si.max_sh_per_se, in si_gpu_init()
3292 rdev->config.si.max_cu_per_sh); in si_gpu_init()
3294 rdev->config.si.active_cus = 0; in si_gpu_init()
3295 for (i = 0; i < rdev->config.si.max_shader_engines; i++) { in si_gpu_init()
3296 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_gpu_init()
3297 rdev->config.si.active_cus += in si_gpu_init()
3312 WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_frontend) | in si_gpu_init()
3313 SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.si.sc_prim_fifo_size_backend) | in si_gpu_init()
3314 SC_HIZ_TILE_FIFO_SIZE(rdev->config.si.sc_hiz_tile_fifo_size) | in si_gpu_init()
3315 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.si.sc_earlyz_tile_fifo_size))); in si_gpu_init()
3569 radeon_ring_write(ring, rdev->config.si.max_hw_contexts - 1); in si_cp_start()
5298 for (i = 0; i < rdev->config.si.max_cu_per_sh; i ++) { in si_get_cu_active_bitmap()
5312 for (i = 0; i < rdev->config.si.max_shader_engines; i++) { in si_init_ao_cu_mask()
5313 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_init_ao_cu_mask()
5317 for (k = 0; k < rdev->config.si.max_cu_per_sh; k++) { in si_init_ao_cu_mask()