2107 	cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;  in si_calculate_cac_wintime()
2668 	reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;  in si_initialize_smc_cac_tables()
2751 			data = RREG32(config_regs->offset << 2);  in si_program_cac_config_registers()
3149 	tmp = RREG32(MC_SEQ_MISC0);  in si_is_special_1gb_platform()
3155 	width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;  in si_is_special_1gb_platform()
3157 	tmp = RREG32(MC_ARB_RAMCFG);  in si_is_special_1gb_platform()
3510 	si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);  in si_read_clock_registers()
3511 	si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);  in si_read_clock_registers()
3512 	si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);  in si_read_clock_registers()
3513 	si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);  in si_read_clock_registers()
3514 	si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);  in si_read_clock_registers()
3515 	si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);  in si_read_clock_registers()
3516 	si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);  in si_read_clock_registers()
3517 	si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);  in si_read_clock_registers()
3518 	si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);  in si_read_clock_registers()
3519 	si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);  in si_read_clock_registers()
3520 	si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);  in si_read_clock_registers()
3521 	si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);  in si_read_clock_registers()
3522 	si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);  in si_read_clock_registers()
3523 	si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);  in si_read_clock_registers()
3524 	si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);  in si_read_clock_registers()
3560 		if (RREG32(SMC_RESP_0) == 1)
3625 	tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);  in si_program_display_gap()
3638 	tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);  in si_program_display_gap()
3739 	u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);  in si_enable_display_gap()
4218 	u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;  in si_calculate_memory_refresh_rate()
4225 	dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);  in si_calculate_memory_refresh_rate()
4246 	dram_timing  = RREG32(MC_ARB_DRAM_TIMING);  in si_populate_memory_timing_parameters()
4247 	dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);  in si_populate_memory_timing_parameters()
4248 	burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;  in si_populate_memory_timing_parameters()
4942 	    (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&  in si_convert_power_level_to_smc()
4961 			    ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))  in si_convert_power_level_to_smc()
4962 				dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;  in si_convert_power_level_to_smc()
4964 				dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;  in si_convert_power_level_to_smc()
4972 		dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;  in si_convert_power_level_to_smc()
5306 			temp_reg = RREG32(MC_PMG_CMD_EMRS);  in si_set_mc_special_registers()
5317 			temp_reg = RREG32(MC_PMG_CMD_MRS);  in si_set_mc_special_registers()
5343 			temp_reg = RREG32(MC_PMG_CMD_MRS1);  in si_set_mc_special_registers()
5483 	WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));  in si_initialize_mc_reg_table()
5484 	WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));  in si_initialize_mc_reg_table()
5485 	WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));  in si_initialize_mc_reg_table()
5486 	WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));  in si_initialize_mc_reg_table()
5487 	WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));  in si_initialize_mc_reg_table()
5488 	WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));  in si_initialize_mc_reg_table()
5489 	WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));  in si_initialize_mc_reg_table()
5490 	WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));  in si_initialize_mc_reg_table()
5491 	WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));  in si_initialize_mc_reg_table()
5492 	WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));  in si_initialize_mc_reg_table()
5493 	WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));  in si_initialize_mc_reg_table()
5494 	WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));  in si_initialize_mc_reg_table()
5495 	WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));  in si_initialize_mc_reg_table()
5496 	WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));  in si_initialize_mc_reg_table()
5882 	u32 thermal_int = RREG32(CG_THERMAL_INT);  in si_thermal_enable_alert()
5935 		tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;  in si_fan_ctrl_set_static_mode()
5937 		tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;  in si_fan_ctrl_set_static_mode()
5942 	tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;  in si_fan_ctrl_set_static_mode()
5946 	tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;  in si_fan_ctrl_set_static_mode()
5967 	duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;  in si_thermal_setup_fan_table()
6011 	tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;  in si_thermal_setup_fan_table()
6066 	duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;  in si_fan_ctrl_get_fan_speed_percent()
6067 	duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;  in si_fan_ctrl_get_fan_speed_percent()
6099 	duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;  in si_fan_ctrl_set_fan_speed_percent()
6108 	tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;  in si_fan_ctrl_set_fan_speed_percent()
6139 	tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;  in si_fan_ctrl_get_mode()
6156 	tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6185 	tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6201 		tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;  in si_fan_ctrl_set_default_mode()
6205 		tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;  in si_fan_ctrl_set_default_mode()
6225 		tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;  in si_thermal_initialize()
6230 	tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;  in si_thermal_initialize()
6990 		(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>  in si_dpm_debugfs_print_current_performance_level()
7010 		(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>  in si_dpm_get_current_sclk()
7028 		(RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>  in si_dpm_get_current_mclk()