2670 	WREG32(CG_CAC_CTRL, reg);  in si_initialize_smc_cac_tables()
2765 			WREG32(config_regs->offset << 2, data);  in si_program_cac_config_registers()
3154 	WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);  in si_is_special_1gb_platform()
3326 	WREG32(SMC_SCRATCH0, parameter);  in si_send_msg_to_smc_with_parameter()
3544 	WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3555 	WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3636 	WREG32(CG_DISPLAY_GAP_CNTL, tmp);  in si_program_display_gap()
3655 		WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);  in si_program_display_gap()
3699 	WREG32(CG_BSP, pi->dsp);  in si_setup_bsp()
3713 		WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));  in si_program_tp()
3729 	WREG32(CG_TPC, R600_TPC_DFLT);  in si_program_tpp()
3734 	WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));  in si_program_sstp()
3748 	WREG32(CG_DISPLAY_GAP_CNTL, tmp);  in si_enable_display_gap()
3755 	WREG32(CG_FTV, pi->vrc);  in si_program_vc()
3760 	WREG32(CG_FTV, 0);  in si_clear_vc()
4706 		WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);  in si_init_smc_table()
4707 		WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);  in si_init_smc_table()
5483 	WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));  in si_initialize_mc_reg_table()
5484 	WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));  in si_initialize_mc_reg_table()
5485 	WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));  in si_initialize_mc_reg_table()
5486 	WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));  in si_initialize_mc_reg_table()
5487 	WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));  in si_initialize_mc_reg_table()
5488 	WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));  in si_initialize_mc_reg_table()
5489 	WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));  in si_initialize_mc_reg_table()
5490 	WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));  in si_initialize_mc_reg_table()
5491 	WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));  in si_initialize_mc_reg_table()
5492 	WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));  in si_initialize_mc_reg_table()
5493 	WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));  in si_initialize_mc_reg_table()
5494 	WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));  in si_initialize_mc_reg_table()
5495 	WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));  in si_initialize_mc_reg_table()
5496 	WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));  in si_initialize_mc_reg_table()
5888 		WREG32(CG_THERMAL_INT, thermal_int);  in si_thermal_enable_alert()
5897 		WREG32(CG_THERMAL_INT, thermal_int);  in si_thermal_enable_alert()
5944 	WREG32(CG_FDO_CTRL2, tmp);  in si_fan_ctrl_set_static_mode()
5948 	WREG32(CG_FDO_CTRL2, tmp);  in si_fan_ctrl_set_static_mode()
6110 	WREG32(CG_FDO_CTRL0, tmp);  in si_fan_ctrl_set_fan_speed_percent()
6187 	WREG32(CG_TACH_CTRL, tmp);
6203 		WREG32(CG_FDO_CTRL2, tmp);  in si_fan_ctrl_set_default_mode()
6207 		WREG32(CG_FDO_CTRL2, tmp);  in si_fan_ctrl_set_default_mode()
6227 		WREG32(CG_TACH_CTRL, tmp);  in si_thermal_initialize()
6232 	WREG32(CG_FDO_CTRL2, tmp);  in si_thermal_initialize()