Lines Matching refs:mclk
2943 u32 mclk, sclk; in si_apply_state_adjust_rules() local
2983 if (ps->performance_levels[i].mclk > max_limits->mclk) in si_apply_state_adjust_rules()
2984 ps->performance_levels[i].mclk = max_limits->mclk; in si_apply_state_adjust_rules()
3008 if (ps->performance_levels[i].mclk > max_mclk_vddci) in si_apply_state_adjust_rules()
3009 ps->performance_levels[i].mclk = max_mclk_vddci; in si_apply_state_adjust_rules()
3012 if (ps->performance_levels[i].mclk > max_mclk_vddc) in si_apply_state_adjust_rules()
3013 ps->performance_levels[i].mclk = max_mclk_vddc; in si_apply_state_adjust_rules()
3016 if (ps->performance_levels[i].mclk > max_mclk) in si_apply_state_adjust_rules()
3017 ps->performance_levels[i].mclk = max_mclk; in si_apply_state_adjust_rules()
3028 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; in si_apply_state_adjust_rules()
3031 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3045 ps->performance_levels[0].mclk = mclk; in si_apply_state_adjust_rules()
3069 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3071 if (mclk < ps->performance_levels[i].mclk) in si_apply_state_adjust_rules()
3072 mclk = ps->performance_levels[i].mclk; in si_apply_state_adjust_rules()
3075 ps->performance_levels[i].mclk = mclk; in si_apply_state_adjust_rules()
3080 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) in si_apply_state_adjust_rules()
3081 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; in si_apply_state_adjust_rules()
3096 ps->performance_levels[i].mclk, in si_apply_state_adjust_rules()
3099 ps->performance_levels[i].mclk, in si_apply_state_adjust_rules()
3798 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) in si_get_strobe_mode_settings() argument
3804 if (mclk <= pi->mclk_strobe_mode_threshold) in si_get_strobe_mode_settings()
3808 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); in si_get_strobe_mode_settings()
3810 result = si_get_ddr3_mclk_frequency_ratio(mclk); in si_get_strobe_mode_settings()
4069 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, in si_populate_mvdd_value() argument
4076 if (mclk <= pi->mvdd_split_frequency) in si_populate_mvdd_value()
4149 u16 voltage, u32 sclk, u32 mclk, in si_populate_phase_shedding_value() argument
4157 (mclk <= limits->entries[i].mclk)) in si_populate_phase_shedding_value()
4244 pl->mclk); in si_populate_memory_timing_parameters()
4315 table->initialState.levels[0].mclk.vDLL_CNTL = in si_populate_smc_initial_state()
4317 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = in si_populate_smc_initial_state()
4319 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = in si_populate_smc_initial_state()
4321 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = in si_populate_smc_initial_state()
4323 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = in si_populate_smc_initial_state()
4325 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = in si_populate_smc_initial_state()
4327 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = in si_populate_smc_initial_state()
4329 table->initialState.levels[0].mclk.vMPLL_SS = in si_populate_smc_initial_state()
4331 table->initialState.levels[0].mclk.vMPLL_SS2 = in si_populate_smc_initial_state()
4334 table->initialState.levels[0].mclk.mclk_value = in si_populate_smc_initial_state()
4335 cpu_to_be32(initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4385 initial_state->performance_levels[0].mclk, in si_populate_smc_initial_state()
4400 initial_state->performance_levels[0].mclk); in si_populate_smc_initial_state()
4402 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) in si_populate_smc_initial_state()
4517 table->ACPIState.levels[0].mclk.vDLL_CNTL = in si_populate_smc_acpi_state()
4519 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = in si_populate_smc_acpi_state()
4521 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = in si_populate_smc_acpi_state()
4523 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = in si_populate_smc_acpi_state()
4525 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = in si_populate_smc_acpi_state()
4527 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = in si_populate_smc_acpi_state()
4529 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = in si_populate_smc_acpi_state()
4531 table->ACPIState.levels[0].mclk.vMPLL_SS = in si_populate_smc_acpi_state()
4533 table->ACPIState.levels[0].mclk.vMPLL_SS2 = in si_populate_smc_acpi_state()
4545 table->ACPIState.levels[0].mclk.mclk_value = 0; in si_populate_smc_acpi_state()
4814 SISLANDS_SMC_MCLK_VALUE *mclk, in si_populate_mclk_value() argument
4886 mclk->mclk_value = cpu_to_be32(memory_clock); in si_populate_mclk_value()
4887 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); in si_populate_mclk_value()
4888 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); in si_populate_mclk_value()
4889 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); in si_populate_mclk_value()
4890 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in si_populate_mclk_value()
4891 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in si_populate_mclk_value()
4892 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in si_populate_mclk_value()
4893 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); in si_populate_mclk_value()
4894 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); in si_populate_mclk_value()
4895 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); in si_populate_mclk_value()
4940 (pl->mclk <= pi->mclk_stutter_mode_threshold) && in si_convert_power_level_to_smc()
4951 if (pl->mclk > pi->mclk_edc_enable_threshold) in si_convert_power_level_to_smc()
4954 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) in si_convert_power_level_to_smc()
4957 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); in si_convert_power_level_to_smc()
4960 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= in si_convert_power_level_to_smc()
4970 pl->mclk); in si_convert_power_level_to_smc()
4977 pl->mclk, in si_convert_power_level_to_smc()
4978 &level->mclk, in si_convert_power_level_to_smc()
5011 pl->mclk, in si_convert_power_level_to_smc()
5019 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); in si_convert_power_level_to_smc()
5093 if (state->performance_levels[0].mclk != ulv->pl.mclk) in si_is_state_ulv_compatible()
5563 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in si_convert_mc_reg_table_entry_to_smc()
6668 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); in si_parse_pplib_clock_info()
6669 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; in si_parse_pplib_clock_info()
6712 pl->mclk = rdev->clock.default_mclk; in si_parse_pplib_clock_info()
6722 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in si_parse_pplib_clock_info()
6960 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) in si_dpm_init()
6999 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); in si_dpm_debugfs_print_current_performance_level()
7035 return pl->mclk; in si_dpm_get_current_mclk()